{"id":"https://openalex.org/W2793681642","doi":"https://doi.org/10.1587/transinf.2017edl8229","title":"Pipelined Squarer for Unsigned Integers of Up to 12 Bits","display_name":"Pipelined Squarer for Unsigned Integers of Up to 12 Bits","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2793681642","doi":"https://doi.org/10.1587/transinf.2017edl8229","mag":"2793681642"},"language":"en","primary_location":{"id":"doi:10.1587/transinf.2017edl8229","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2017edl8229","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E101.D/3/E101.D_2017EDL8229/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/transinf/E101.D/3/E101.D_2017EDL8229/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082634431","display_name":"Seongjin Choi","orcid":"https://orcid.org/0000-0001-7140-537X"},"institutions":[{"id":"https://openalex.org/I4210161052","display_name":"Korea University","ror":"https://ror.org/05m1gnk07","country_code":"JP","type":"education","lineage":["https://openalex.org/I4210161052"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Seongjin CHOI","raw_affiliation_strings":["College of Sci. & Tech., Korea Univ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Sci. & Tech., Korea Univ","institution_ids":["https://openalex.org/I4210161052"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108414284","display_name":"Hyeong-Cheol Oh","orcid":null},"institutions":[{"id":"https://openalex.org/I4210161052","display_name":"Korea University","ror":"https://ror.org/05m1gnk07","country_code":"JP","type":"education","lineage":["https://openalex.org/I4210161052"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hyeong-Cheol OH","raw_affiliation_strings":["College of Sci. & Tech., Korea Univ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Sci. & Tech., Korea Univ","institution_ids":["https://openalex.org/I4210161052"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1309,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.46095753,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"E101.D","issue":"3","first_page":"795","last_page":"798"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8440269827842712},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7939321994781494},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.7490406036376953},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6871838569641113},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5567938089370728},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5115936398506165},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48620858788490295},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.48287108540534973},{"id":"https://openalex.org/keywords/square","display_name":"Square (algebra)","score":0.47722747921943665},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4695364236831665},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4682252109050751},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.348981112241745},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3313223421573639},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14275112748146057},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.0718737244606018},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06353282928466797},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.059548795223236084}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8440269827842712},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7939321994781494},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.7490406036376953},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6871838569641113},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5567938089370728},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5115936398506165},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48620858788490295},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.48287108540534973},{"id":"https://openalex.org/C135692309","wikidata":"https://www.wikidata.org/wiki/Q111124","display_name":"Square (algebra)","level":2,"score":0.47722747921943665},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4695364236831665},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4682252109050751},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.348981112241745},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3313223421573639},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14275112748146057},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0718737244606018},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06353282928466797},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.059548795223236084},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transinf.2017edl8229","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2017edl8229","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E101.D/3/E101.D_2017EDL8229/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/transinf.2017edl8229","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2017edl8229","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E101.D/3/E101.D_2017EDL8229/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321373","display_name":"Korea University","ror":"https://ror.org/047dqcg40"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2793681642.pdf","grobid_xml":"https://content.openalex.org/works/W2793681642.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W1570834090","https://openalex.org/W1966139910","https://openalex.org/W1981371093","https://openalex.org/W2054559616","https://openalex.org/W2069360272","https://openalex.org/W2073393819","https://openalex.org/W2158413252","https://openalex.org/W2166628680","https://openalex.org/W2591922920","https://openalex.org/W2851328330","https://openalex.org/W2855252954","https://openalex.org/W3140847110"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W1509155667","https://openalex.org/W2518118925","https://openalex.org/W3208151864","https://openalex.org/W1564576805","https://openalex.org/W4254372399"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"and":[3,26,35],"analyzes":[4],"a":[5,9,70],"pipelining":[6],"scheme":[7],"for":[8],"hardware":[10],"squarer":[11,94],"that":[12,29,36],"can":[13],"square":[14],"unsigned":[15],"integers":[16],"of":[17,41,66],"up":[18,53],"to":[19],"12":[20],"bits.":[21],"Each":[22],"stage":[23,30],"is":[24,51],"designed":[25],"adjusted":[27],"such":[28],"delays":[31],"are":[32],"well":[33],"balanced":[34],"the":[37,42,47,56,62,82,91,97],"critical":[38,63],"path":[39,64],"delay":[40,65],"design":[43,60,83],"does":[44],"not":[45],"exceed":[46],"reference":[48],"value":[49],"which":[50],"set":[52],"based":[54],"on":[55],"analysis.":[57],"The":[58],"resultant":[59],"has":[61],"approximately":[67,86],"3.5":[68],"times":[69],"full-adder":[71],"delay.":[72],"In":[73],"an":[74,77],"implementation":[75],"using":[76],"Intel":[78,98],"Stratix":[79],"V":[80],"FPGA,":[81],"operates":[84],"at":[85],"23%":[87],"higher":[88],"frequency":[89],"than":[90],"comparable":[92],"pipelined":[93],"provided":[95],"in":[96],"library.":[99]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}