{"id":"https://openalex.org/W2597751488","doi":"https://doi.org/10.1587/transinf.2016awi0005","title":"Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core","display_name":"Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core","publication_year":2017,"publication_date":"2017-01-01","ids":{"openalex":"https://openalex.org/W2597751488","doi":"https://doi.org/10.1587/transinf.2016awi0005","mag":"2597751488"},"language":"en","primary_location":{"id":"doi:10.1587/transinf.2016awi0005","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2016awi0005","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E100.D/4/E100.D_2016AWI0005/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/transinf/E100.D/4/E100.D_2016AWI0005/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012465812","display_name":"Motoki Amagasaki","orcid":"https://orcid.org/0000-0002-5196-9765"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Motoki AMAGASAKI","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005918658","display_name":"Yuki Nishitani","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuki NISHITANI","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102114017","display_name":"Kazuki Inoue","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuki INOUE","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059705629","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9654-2319"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro IIDA","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109427367","display_name":"Morihiro Kuga","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Morihiro KUGA","raw_affiliation_strings":["Faculty of Advanced Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031401749","display_name":"Toshinori Sueyoshi","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshinori SUEYOSHI","raw_affiliation_strings":["Faculty of Advanced Science and Technology, Kumamoto University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Technology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.02637034,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"E100.D","issue":"4","first_page":"633","last_page":"644"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8492504358291626},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7949922680854797},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6255745887756348},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.5116636753082275},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35479867458343506},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33162540197372437},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09432077407836914}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8492504358291626},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7949922680854797},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6255745887756348},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.5116636753082275},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35479867458343506},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33162540197372437},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09432077407836914}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transinf.2016awi0005","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2016awi0005","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E100.D/4/E100.D_2016AWI0005/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/transinf.2016awi0005","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transinf.2016awi0005","pdf_url":"https://www.jstage.jst.go.jp/article/transinf/E100.D/4/E100.D_2016AWI0005/_pdf","source":{"id":"https://openalex.org/S2486202937","display_name":"IEICE Transactions on Information and Systems","issn_l":"0916-8532","issn":["0916-8532","1745-1361"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Information and Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/13","display_name":"Climate action","score":0.5799999833106995}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309545","display_name":"Synopsys","ror":"https://ror.org/013by2m91"},{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2597751488.pdf","grobid_xml":"https://content.openalex.org/works/W2597751488.grobid-xml"},"referenced_works_count":18,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1594667974","https://openalex.org/W1831088354","https://openalex.org/W1993237560","https://openalex.org/W2010995573","https://openalex.org/W2034034477","https://openalex.org/W2035176666","https://openalex.org/W2035847677","https://openalex.org/W2068920660","https://openalex.org/W2075977842","https://openalex.org/W2076930138","https://openalex.org/W2088559447","https://openalex.org/W2105011467","https://openalex.org/W2118476171","https://openalex.org/W2119901643","https://openalex.org/W2137235679","https://openalex.org/W2150629048","https://openalex.org/W4206262605"],"related_works":["https://openalex.org/W2002703587","https://openalex.org/W3217667592","https://openalex.org/W1968329900","https://openalex.org/W3094426418","https://openalex.org/W2373066471","https://openalex.org/W1508811950","https://openalex.org/W4366380722","https://openalex.org/W2380210889","https://openalex.org/W2379107344","https://openalex.org/W2350474477"],"abstract_inverted_index":{"Fault":[0],"tolerance":[1],"is":[2],"an":[3,66],"important":[4],"feature":[5],"for":[6,125],"the":[7,46,59,96,114,126,131,148,151],"system":[8,132],"LSIs":[9],"used":[10,19],"in":[11,70,101,130,150],"reliability-critical":[12],"systems.":[13],"Although":[14],"redundancy":[15],"techniques":[16,25],"are":[17],"generally":[18],"to":[20,38,54,95,139,147],"provide":[21,34],"fault":[22,79,89,106,111,144],"tolerance,":[23],"these":[24],"have":[26],"significantly":[27],"hardware":[28],"costs.":[29],"However,":[30],"FPGAs":[31],"can":[32,49],"easily":[33],"high":[35],"reliability":[36],"due":[37],"their":[39],"reconfiguration":[40],"ability.":[41],"Even":[42],"if":[43],"faults":[44,149],"occur,":[45],"implemented":[47],"circuit":[48],"perform":[50,110],"correctly":[51],"by":[52],"reconfiguring":[53],"a":[55,74,84,93],"fault-free":[56],"region":[57],"of":[58],"FPGA.":[60],"In":[61],"this":[62],"paper,":[63],"we":[64,91,109],"examine":[65],"FPGA-IP":[67,127],"core":[68,128],"loaded":[69,129],"SoC":[71],"and":[72,81,104,117,142],"introduce":[73],"fault-tolerant":[75],"technology":[76],"based":[77],"on":[78],"detection":[80],"recovery":[82,112],"as":[83],"CAD-level":[85],"approach.":[86],"To":[87],"detect":[88],"position,":[90],"add":[92],"route":[94],"manufacturing":[97],"test":[98],"method":[99],"proposed":[100],"earlier":[102],"research":[103],"identify":[105,141],"areas.":[107],"Furthermore,":[108],"at":[113],"logic":[115],"tile":[116],"multiplexer":[118],"levels":[119],"using":[120],"reconfiguration.":[121],"The":[122],"evaluation":[123],"results":[124],"LSI":[133],"demonstrate":[134],"that":[135],"it":[136],"was":[137],"able":[138],"completely":[140],"avoid":[143],"areas":[145],"relative":[146],"routing":[152],"area.":[153]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}