{"id":"https://openalex.org/W2087111304","doi":"https://doi.org/10.1587/transfun.e92.a.1031","title":"Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits","display_name":"Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W2087111304","doi":"https://doi.org/10.1587/transfun.e92.a.1031","mag":"2087111304"},"language":"en","primary_location":{"id":"doi:10.1587/transfun.e92.a.1031","is_oa":false,"landing_page_url":"https://doi.org/10.1587/transfun.e92.a.1031","pdf_url":null,"source":{"id":"https://openalex.org/S166990724","display_name":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences","issn_l":"0916-8508","issn":["0916-8508","1745-1337"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066562431","display_name":"Shiho Hagiwara","orcid":"https://orcid.org/0000-0002-1659-7134"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Shiho HAGIWARA","raw_affiliation_strings":["Integrated Research Institute, Tokyo Institute of Technology","Integrated research institute, Tokyo Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Integrated Research Institute, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Integrated research institute, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017861176","display_name":"Takashi Sat\u014d","orcid":"https://orcid.org/0000-0002-1577-8259"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takashi SATO","raw_affiliation_strings":["Integrated Research Institute, Tokyo Institute of Technology","Integrated research institute, Tokyo Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Integrated Research Institute, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Integrated research institute, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049015548","display_name":"Kazuya Masu","orcid":"https://orcid.org/0000-0002-7121-8440"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuya MASU","raw_affiliation_strings":["Integrated Research Institute, Tokyo Institute of Technology","Integrated research institute, Tokyo Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Integrated Research Institute, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]},{"raw_affiliation_string":"Integrated research institute, Tokyo Institute of Technology","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5066562431"],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11792483,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"E92-A","issue":"4","first_page":"1031","last_page":"1038"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7117193937301636},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6921044588088989},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6238585710525513},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.597536563873291},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5518421530723572},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.539448618888855},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.5278798341751099},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4912185072898865},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4340939223766327},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.41050219535827637},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.36781829595565796},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22884207963943481},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20388349890708923},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18157550692558289},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10798722505569458},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.07483020424842834}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7117193937301636},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6921044588088989},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6238585710525513},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.597536563873291},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5518421530723572},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.539448618888855},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.5278798341751099},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4912185072898865},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4340939223766327},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.41050219535827637},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.36781829595565796},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22884207963943481},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20388349890708923},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18157550692558289},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10798722505569458},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.07483020424842834},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transfun.e92.a.1031","is_oa":false,"landing_page_url":"https://doi.org/10.1587/transfun.e92.a.1031","pdf_url":null,"source":{"id":"https://openalex.org/S166990724","display_name":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences","issn_l":"0916-8508","issn":["0916-8508","1745-1337"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6600000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1591241315","https://openalex.org/W2004934210","https://openalex.org/W2096351140","https://openalex.org/W2108923470","https://openalex.org/W2109797003","https://openalex.org/W2114621701","https://openalex.org/W2116831899","https://openalex.org/W2126564504","https://openalex.org/W2126811283","https://openalex.org/W2178225970","https://openalex.org/W3152237812","https://openalex.org/W4237955880"],"related_works":["https://openalex.org/W3015599398","https://openalex.org/W2188730438","https://openalex.org/W2157230896","https://openalex.org/W2792778858","https://openalex.org/W2034656493","https://openalex.org/W2129873400","https://openalex.org/W2572576974","https://openalex.org/W2362904186","https://openalex.org/W3008786049","https://openalex.org/W98453623"],"abstract_inverted_index":{"Circuits":[0],"utilizing":[1],"advanced":[2],"process":[3,46,129],"technologies":[4],"have":[5],"to":[6,13,79],"correctly":[7],"account":[8],"for":[9,22,122],"device":[10],"parameter":[11,83],"variation":[12,26,42,106],"optimize":[14],"its":[15,41],"performance.":[16],"In":[17],"this":[18],"paper,":[19],"analytical":[20],"formulas":[21,36,92,118],"evaluating":[23],"path":[24,38,104],"delay":[25,39,105],"of":[27,45,89,102,113,125],"Multi-Threshold":[28],"CMOS":[29],"(MTCMOS)":[30],"circuits":[31,127],"are":[32,49,64,93,119],"proposed.":[33],"The":[34,116],"proposed":[35,91,98,117],"express":[37],"and":[40,59,72],"as":[43],"functions":[44],"parameters":[47,62],"that":[48,63,112],"determined":[50,65],"by":[51,66],"fabrication":[52],"technology":[53],"(threshold":[54],"voltage,":[55],"carrier":[56],"mobility,":[57],"etc.)":[58],"the":[60,73,81,87,90,97],"circuit":[61,67,82],"structure":[68],"(equivalent":[69],"load":[70],"capacitance":[71],"concurrently":[74],"switching":[75],"gates).":[76],"Two":[77],"procedures":[78],"obtain":[80],"sets":[84],"necessary":[85],"in":[86],"calculation":[88,100],"also":[94],"defined.":[95],"With":[96],"formulas,":[99],"time":[101],"a":[103],"becomes":[107],"three":[108],"orders":[109],"faster":[110],"than":[111],"Monte-Carlo":[114],"simulation.":[115],"suitably":[120],"applied":[121],"efficient":[123],"design":[124],"MTCMOS":[126],"considering":[128],"variation.":[130]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
