{"id":"https://openalex.org/W4312549670","doi":"https://doi.org/10.1587/transfun.2022vlp0008","title":"An eFPGA Generation Suite with Customizable Architecture and IDE","display_name":"An eFPGA Generation Suite with Customizable Architecture and IDE","publication_year":2022,"publication_date":"2022-10-06","ids":{"openalex":"https://openalex.org/W4312549670","doi":"https://doi.org/10.1587/transfun.2022vlp0008"},"language":"en","primary_location":{"id":"doi:10.1587/transfun.2022vlp0008","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transfun.2022vlp0008","pdf_url":"https://www.jstage.jst.go.jp/article/transfun/E106.A/3/E106.A_2022VLP0008/_pdf","source":{"id":"https://openalex.org/S166990724","display_name":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences","issn_l":"0916-8508","issn":["0916-8508","1745-1337"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://www.jstage.jst.go.jp/article/transfun/E106.A/3/E106.A_2022VLP0008/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109427367","display_name":"Morihiro Kuga","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Morihiro KUGA","raw_affiliation_strings":["Faculty of Advanced Science and Thechnology, Kumamoto University"],"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Thechnology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051831948","display_name":"Qian Zhao","orcid":"https://orcid.org/0000-0003-0032-1974"},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Qian ZHAO","raw_affiliation_strings":["Kyushu Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Kyushu Institute of Technology","institution_ids":["https://openalex.org/I207014233"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074521540","display_name":"Yuya Nakazato","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuya NAKAZATO","raw_affiliation_strings":["Dept. of Graduate School of Science and Thechnology, Kumamoto University"],"affiliations":[{"raw_affiliation_string":"Dept. of Graduate School of Science and Thechnology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012465812","display_name":"Motoki Amagasaki","orcid":"https://orcid.org/0000-0002-5196-9765"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Motoki AMAGASAKI","raw_affiliation_strings":["Faculty of Advanced Science and Thechnology, Kumamoto University"],"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Thechnology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059705629","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9654-2319"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro IIDA","raw_affiliation_strings":["Faculty of Advanced Science and Thechnology, Kumamoto University"],"affiliations":[{"raw_affiliation_string":"Faculty of Advanced Science and Thechnology, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5109427367"],"corresponding_institution_ids":["https://openalex.org/I96036126"],"apc_list":null,"apc_paid":null,"fwci":1.1357,"has_fulltext":true,"cited_by_count":5,"citation_normalized_percentile":{"value":0.7717796,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":97},"biblio":{"volume":"E106.A","issue":"3","first_page":"560","last_page":"574"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7143017649650574},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6661418080329895},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6552677154541016},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.6113160252571106},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4883108139038086},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4563480317592621},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.4326033592224121},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.4285493791103363},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2253894805908203},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13789838552474976}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7143017649650574},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6661418080329895},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6552677154541016},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.6113160252571106},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4883108139038086},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4563480317592621},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.4326033592224121},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.4285493791103363},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2253894805908203},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13789838552474976},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transfun.2022vlp0008","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transfun.2022vlp0008","pdf_url":"https://www.jstage.jst.go.jp/article/transfun/E106.A/3/E106.A_2022VLP0008/_pdf","source":{"id":"https://openalex.org/S166990724","display_name":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences","issn_l":"0916-8508","issn":["0916-8508","1745-1337"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/transfun.2022vlp0008","is_oa":true,"landing_page_url":"https://doi.org/10.1587/transfun.2022vlp0008","pdf_url":"https://www.jstage.jst.go.jp/article/transfun/E106.A/3/E106.A_2022VLP0008/_pdf","source":{"id":"https://openalex.org/S166990724","display_name":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences","issn_l":"0916-8508","issn":["0916-8508","1745-1337"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.6100000143051147,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320338075","display_name":"Core Research for Evolutional Science and Technology","ror":"https://ror.org/00097mb19"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4312549670.pdf","grobid_xml":"https://content.openalex.org/works/W4312549670.grobid-xml"},"referenced_works_count":20,"referenced_works":["https://openalex.org/W1669114967","https://openalex.org/W1831088354","https://openalex.org/W1993232175","https://openalex.org/W2075977842","https://openalex.org/W2093426958","https://openalex.org/W2109656299","https://openalex.org/W2113469110","https://openalex.org/W2113645429","https://openalex.org/W2114181278","https://openalex.org/W2133743520","https://openalex.org/W2138383740","https://openalex.org/W2146056883","https://openalex.org/W2559278389","https://openalex.org/W2597751488","https://openalex.org/W3027559990","https://openalex.org/W3129912126","https://openalex.org/W3130402546","https://openalex.org/W3132470343","https://openalex.org/W3143008962","https://openalex.org/W3177261938"],"related_works":["https://openalex.org/W2091330445","https://openalex.org/W2109907925","https://openalex.org/W4247963789","https://openalex.org/W2051573100","https://openalex.org/W2045973193","https://openalex.org/W1994293185","https://openalex.org/W2542547697","https://openalex.org/W2100322987","https://openalex.org/W2607447167","https://openalex.org/W4236604936"],"abstract_inverted_index":{"From":[0],"edge":[1],"devices":[2],"to":[3,18,34,64,81],"cloud":[4],"servers,":[5],"providing":[6],"optimized":[7],"hardware":[8,37,74],"acceleration":[9],"for":[10,76,145,184,205],"specific":[11,78],"applications":[12],"has":[13],"become":[14],"a":[15,77,85,154,177,206,227],"key":[16],"approach":[17],"improve":[19],"the":[20,40,55,90,115,125,137,150,170,185,190,195,212,218,223],"efficiency":[21],"of":[22,57,92,222],"computer":[23],"systems.":[24],"Traditionally,":[25],"many":[26],"systems":[27],"employ":[28,153],"commercial":[29,44],"field-programmable":[30],"gate":[31],"arrays":[32],"(FPGAs)":[33],"implement":[35],"dedicated":[36],"accelerator":[38],"as":[39,71],"CPU's":[41],"co-processor.":[42],"However,":[43],"FPGAs":[45],"are":[46,52],"designed":[47],"in":[48,54,89,169],"generic":[49],"architectures":[50],"and":[51,108,121,142,179,220],"provided":[53],"form":[56,91],"discrete":[58],"chips,":[59],"which":[60,113],"makes":[61],"it":[62],"difficult":[63],"meet":[65],"increasingly":[66],"diversified":[67],"market":[68],"needs,":[69],"such":[70],"balancing":[72],"reconfigurable":[73],"resources":[75],"application,":[79],"or":[80],"be":[82],"integrated":[83,109],"into":[84],"customer's":[86],"system-on-a-chip":[87],"(SoC)":[88],"embedded":[93],"FPGA":[94],"(eFPGA).":[95],"In":[96,173,194],"this":[97],"paper,":[98],"we":[99,152,175,198,216],"propose":[100,176],"an":[101,200],"eFPGA":[102,117,126,187,201,224],"generation":[103,133],"suite":[104],"with":[105,226],"customizable":[106,180],"architecture":[107,202],"development":[110,192],"environment":[111],"(IDE),":[112],"covers":[114],"entire":[116,171],"design":[118,127],"generation,":[119,128],"testing,":[120],"utilization":[122],"stages.":[123],"For":[124,149],"our":[129],"intellectual":[130],"property":[131],"(IP)":[132],"flow":[134],"can":[135],"explore":[136],"optimal":[138],"logic":[139],"cell,":[140],"routing,":[141],"array":[143],"structures":[144],"given":[146],"target":[147],"applications.":[148],"testability,":[151],"previously":[155],"proposed":[156,213],"shipping":[157],"test":[158,229],"method":[159],"that":[160],"is":[161],"100%":[162],"accurate":[163],"at":[164],"detecting":[165],"all":[166],"stuck-at":[167],"faults":[168],"FPGA-IP.":[172],"addition,":[174],"user-friendly":[178],"Web-based":[181],"IDE":[182],"framework":[183],"generated":[186],"based":[188],"on":[189],"NODE-RED":[191],"framework.":[193],"case":[196],"study,":[197],"show":[199,217],"exploration":[203],"example":[204],"differential":[207],"privacy":[208],"encryption":[209],"application":[210],"using":[211],"suite.":[214],"Then":[215],"implementation":[219],"evaluation":[221],"prototype":[225],"55nm":[228],"element":[230],"group":[231],"chip":[232],"design.":[233]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}