{"id":"https://openalex.org/W3032833143","doi":"https://doi.org/10.1587/transfun.2019eap1146","title":"Supporting Predictable Performance Guarantees for SMT Processors","display_name":"Supporting Predictable Performance Guarantees for SMT Processors","publication_year":2020,"publication_date":"2020-05-31","ids":{"openalex":"https://openalex.org/W3032833143","doi":"https://doi.org/10.1587/transfun.2019eap1146","mag":"3032833143"},"language":"en","primary_location":{"id":"doi:10.1587/transfun.2019eap1146","is_oa":false,"landing_page_url":"https://doi.org/10.1587/transfun.2019eap1146","pdf_url":null,"source":{"id":"https://openalex.org/S166990724","display_name":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences","issn_l":"0916-8508","issn":["0916-8508","1745-1337"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033127079","display_name":"Xin Jin","orcid":"https://orcid.org/0000-0003-0935-5329"},"institutions":[{"id":"https://openalex.org/I4210131919","display_name":"Xi'an University of Technology","ror":"https://ror.org/038avdt50","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210131919"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin JIN","raw_affiliation_strings":["Faculty of Automation and Information Engineering, Xi'an University of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Automation and Information Engineering, Xi'an University of Technology","institution_ids":["https://openalex.org/I4210131919"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101680857","display_name":"Ningmei Yu","orcid":"https://orcid.org/0000-0002-4219-8364"},"institutions":[{"id":"https://openalex.org/I4210131919","display_name":"Xi'an University of Technology","ror":"https://ror.org/038avdt50","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210131919"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ningmei YU","raw_affiliation_strings":["Faculty of Automation and Information Engineering, Xi'an University of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Automation and Information Engineering, Xi'an University of Technology","institution_ids":["https://openalex.org/I4210131919"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063691094","display_name":"Yaoyang Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I4391767888","display_name":"State Key Laboratory of Computer Architecture","ror":"https://ror.org/02pq9w205","country_code":null,"type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176","https://openalex.org/I4391767888"]}],"countries":[],"is_corresponding":false,"raw_author_name":"Yaoyang ZHOU","raw_affiliation_strings":["State Key Laboratory of Computer Architecture, ICT, CAS"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, ICT, CAS","institution_ids":["https://openalex.org/I4391767888"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042136632","display_name":"Bowen Huang","orcid":"https://orcid.org/0000-0002-2682-9584"},"institutions":[{"id":"https://openalex.org/I4391767888","display_name":"State Key Laboratory of Computer Architecture","ror":"https://ror.org/02pq9w205","country_code":null,"type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176","https://openalex.org/I4391767888"]}],"countries":[],"is_corresponding":false,"raw_author_name":"Bowen HUANG","raw_affiliation_strings":["State Key Laboratory of Computer Architecture, ICT, CAS"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, ICT, CAS","institution_ids":["https://openalex.org/I4391767888"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100324772","display_name":"Zihao Yu","orcid":"https://orcid.org/0000-0001-7847-3359"},"institutions":[{"id":"https://openalex.org/I4391767888","display_name":"State Key Laboratory of Computer Architecture","ror":"https://ror.org/02pq9w205","country_code":null,"type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176","https://openalex.org/I4391767888"]}],"countries":[],"is_corresponding":false,"raw_author_name":"Zihao YU","raw_affiliation_strings":["State Key Laboratory of Computer Architecture, ICT, CAS"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, ICT, CAS","institution_ids":["https://openalex.org/I4391767888"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038878791","display_name":"Xusheng Zhan","orcid":null},"institutions":[{"id":"https://openalex.org/I4391767888","display_name":"State Key Laboratory of Computer Architecture","ror":"https://ror.org/02pq9w205","country_code":null,"type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176","https://openalex.org/I4391767888"]}],"countries":[],"is_corresponding":false,"raw_author_name":"Xusheng ZHAN","raw_affiliation_strings":["State Key Laboratory of Computer Architecture, ICT, CAS"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, ICT, CAS","institution_ids":["https://openalex.org/I4391767888"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025473989","display_name":"Huizhe Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I4391767888","display_name":"State Key Laboratory of Computer Architecture","ror":"https://ror.org/02pq9w205","country_code":null,"type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176","https://openalex.org/I4391767888"]}],"countries":[],"is_corresponding":false,"raw_author_name":"Huizhe WANG","raw_affiliation_strings":["State Key Laboratory of Computer Architecture, ICT, CAS"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, ICT, CAS","institution_ids":["https://openalex.org/I4391767888"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101664399","display_name":"Sa Wang","orcid":"https://orcid.org/0000-0003-0451-7181"},"institutions":[{"id":"https://openalex.org/I4391767888","display_name":"State Key Laboratory of Computer Architecture","ror":"https://ror.org/02pq9w205","country_code":null,"type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176","https://openalex.org/I4391767888"]}],"countries":[],"is_corresponding":false,"raw_author_name":"Sa WANG","raw_affiliation_strings":["State Key Laboratory of Computer Architecture, ICT, CAS"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, ICT, CAS","institution_ids":["https://openalex.org/I4391767888"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018915362","display_name":"Bao Yungang","orcid":null},"institutions":[{"id":"https://openalex.org/I4391767888","display_name":"State Key Laboratory of Computer Architecture","ror":"https://ror.org/02pq9w205","country_code":null,"type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176","https://openalex.org/I4391767888"]}],"countries":[],"is_corresponding":false,"raw_author_name":"Yungang BAO","raw_affiliation_strings":["State Key Laboratory of Computer Architecture, ICT, CAS"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, ICT, CAS","institution_ids":["https://openalex.org/I4391767888"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.06564305,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"E103.A","issue":"6","first_page":"806","last_page":"820"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8620914220809937},{"id":"https://openalex.org/keywords/simultaneous-multithreading","display_name":"Simultaneous multithreading","score":0.828305721282959},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.7264629602432251},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.716876208782196},{"id":"https://openalex.org/keywords/workload","display_name":"Workload","score":0.7048488855361938},{"id":"https://openalex.org/keywords/quality-of-service","display_name":"Quality of service","score":0.6117333173751831},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5346713662147522},{"id":"https://openalex.org/keywords/quality","display_name":"Quality (philosophy)","score":0.43600261211395264},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3594607710838318},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.31748396158218384},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2683356702327728},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.19019055366516113},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1267225444316864}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8620914220809937},{"id":"https://openalex.org/C85717602","wikidata":"https://www.wikidata.org/wiki/Q82178","display_name":"Simultaneous multithreading","level":4,"score":0.828305721282959},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.7264629602432251},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.716876208782196},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.7048488855361938},{"id":"https://openalex.org/C5119721","wikidata":"https://www.wikidata.org/wiki/Q220501","display_name":"Quality of service","level":2,"score":0.6117333173751831},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5346713662147522},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.43600261211395264},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3594607710838318},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.31748396158218384},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2683356702327728},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.19019055366516113},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1267225444316864},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transfun.2019eap1146","is_oa":false,"landing_page_url":"https://doi.org/10.1587/transfun.2019eap1146","pdf_url":null,"source":{"id":"https://openalex.org/S166990724","display_name":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences","issn_l":"0916-8508","issn":["0916-8508","1745-1337"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1987275546","https://openalex.org/W2017004353","https://openalex.org/W2036770126","https://openalex.org/W2036853599","https://openalex.org/W2044581440","https://openalex.org/W2064037464","https://openalex.org/W2065262858","https://openalex.org/W2066983200","https://openalex.org/W2067354926","https://openalex.org/W2076828486","https://openalex.org/W2083839254","https://openalex.org/W2093941454","https://openalex.org/W2116020886","https://openalex.org/W2116360965","https://openalex.org/W2118532220","https://openalex.org/W2120230074","https://openalex.org/W2127643746","https://openalex.org/W2129393463","https://openalex.org/W2134323253","https://openalex.org/W2140057257","https://openalex.org/W2144510018","https://openalex.org/W2147657366","https://openalex.org/W2168452045","https://openalex.org/W2170382128","https://openalex.org/W2344981378","https://openalex.org/W2398646962","https://openalex.org/W2999459139","https://openalex.org/W3027220693","https://openalex.org/W3141739369","https://openalex.org/W4239012550","https://openalex.org/W4242220430","https://openalex.org/W4253086812"],"related_works":["https://openalex.org/W2118532220","https://openalex.org/W4240807263","https://openalex.org/W2913446311","https://openalex.org/W1532726325","https://openalex.org/W2115561485","https://openalex.org/W2354938433","https://openalex.org/W3142147837","https://openalex.org/W2294358097","https://openalex.org/W2482815832","https://openalex.org/W3142189107"],"abstract_inverted_index":{"Simultaneous":[0],"multithreading":[1],"(SMT)":[2],"technology":[3],"improves":[4],"CPU":[5],"throughput,":[6],"but":[7,76],"also":[8,77],"causes":[9],"unpredictable":[10],"performance":[11,35,84,127,140],"fluctuations":[12],"for":[13,29,129],"co-running":[14],"workloads.":[15],"Although":[16],"recent":[17],"major":[18],"SMT":[19,41],"processors":[20],"have":[21],"adopted":[22],"some":[23,55],"techniques":[24],"to":[25,99,124],"promote":[26],"hardware":[27,110],"support":[28],"quality-of-service":[30],"(QoS),":[31],"achieving":[32,133],"both":[33],"precise":[34,126],"guarantees":[36,128],"and":[37,85,122,166],"high":[38],"throughput":[39],"on":[40,58,151],"architectures":[42],"is":[43,79,162],"still":[44],"a":[45,59,80,108,114,142,149],"challenging":[46,101],"open":[47],"problem.":[48],"In":[49],"this":[50],"paper,":[51],"we":[52,105],"demonstrate":[53],"through":[54],"comprehensive":[56],"investigations":[57],"cycle-accurate":[60],"simulator":[61],"that":[62,112,157],"not":[63],"only":[64,163],"almost":[65],"all":[66],"in-core":[67],"resources":[68],"suffer":[69],"from":[70],"severe":[71],"contention":[72],"as":[73,94],"workloads":[74],"vary":[75],"there":[78],"non-linear":[81],"relationship":[82],"between":[83],"available":[86],"quotas":[87],"of":[88,119,138,141],"resources.":[89],"We":[90,147],"consider":[91],"these":[92],"observations":[93],"the":[95,100,139,158],"fundamental":[96],"reason":[97],"leading":[98],"problem":[102],"above.":[103],"Thus,":[104],"introduce":[106],"QoSMT,":[107],"novel":[109],"scheme":[111],"leverages":[113],"closed-loop":[115],"controlling":[116],"mechanism":[117],"consisting":[118],"detection,":[120],"prediction":[121],"adjustment":[123],"enforce":[125],"specific":[130],"targets,":[131],"e.g.":[132],"85%,":[134],"90%":[135],"or":[136],"95%":[137],"workload":[143],"running":[144],"alone":[145],"respectively.":[146],"implement":[148],"prototype":[150],"GEM5":[152],"simulator.":[153],"Experimental":[154],"results":[155],"show":[156],"average":[159],"control":[160],"error":[161],"1.4%,":[164],"0.5%":[165],"3.6%.":[167]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
