{"id":"https://openalex.org/W2020740124","doi":"https://doi.org/10.1587/transele.e96.c.501","title":"Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs","display_name":"Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W2020740124","doi":"https://doi.org/10.1587/transele.e96.c.501","mag":"2020740124"},"language":"en","primary_location":{"id":"doi:10.1587/transele.e96.c.501","is_oa":false,"landing_page_url":"https://doi.org/10.1587/transele.e96.c.501","pdf_url":null,"source":{"id":"https://openalex.org/S2489501747","display_name":"IEICE Transactions on Electronics","issn_l":"0916-8524","issn":["0916-8524","1745-1353"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Electronics","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101918577","display_name":"Nan Liu","orcid":"https://orcid.org/0009-0006-7087-6990"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nan LIU","raw_affiliation_strings":["Graduate School of IPS, Waseda University","[Graduate school of IPS, Waseda University]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of IPS, Waseda University","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"[Graduate school of IPS, Waseda University]","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100423614","display_name":"Song Chen","orcid":"https://orcid.org/0000-0003-0341-3428"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Song CHEN","raw_affiliation_strings":["Graduate School of IPS, Waseda University","[Graduate school of IPS, Waseda University]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of IPS, Waseda University","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"[Graduate school of IPS, Waseda University]","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101886411","display_name":"Takeshi Yoshimura","orcid":"https://orcid.org/0000-0002-7147-4225"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takeshi YOSHIMURA","raw_affiliation_strings":["Graduate School of IPS, Waseda University","[Graduate school of IPS, Waseda University]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of IPS, Waseda University","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"[Graduate school of IPS, Waseda University]","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":0.2349,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59491677,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"E96.C","issue":"4","first_page":"501","last_page":"510"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9220250248908997},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8307144641876221},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7752984762191772},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6579757332801819},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5527396202087402},{"id":"https://openalex.org/keywords/resource","display_name":"Resource (disambiguation)","score":0.4351412057876587},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42754143476486206},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3869993984699249},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3868342638015747},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3236704468727112},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08551359176635742}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9220250248908997},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8307144641876221},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7752984762191772},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6579757332801819},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5527396202087402},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.4351412057876587},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42754143476486206},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3869993984699249},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3868342638015747},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3236704468727112},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08551359176635742}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transele.e96.c.501","is_oa":false,"landing_page_url":"https://doi.org/10.1587/transele.e96.c.501","pdf_url":null,"source":{"id":"https://openalex.org/S2489501747","display_name":"IEICE Transactions on Electronics","issn_l":"0916-8524","issn":["0916-8524","1745-1353"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Electronics","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2608986955","display_name":"Floorplan-base Design Environment Technologies for Large-Scale System LSIs","funder_award_id":"23560417","funder_id":"https://openalex.org/F4320334764","funder_display_name":"Japan Society for the Promotion of Science"}],"funders":[{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1497138450","https://openalex.org/W1564544652","https://openalex.org/W1833016444","https://openalex.org/W1978905553","https://openalex.org/W1986707531","https://openalex.org/W2019168206","https://openalex.org/W2030767815","https://openalex.org/W2034729118","https://openalex.org/W2070215512","https://openalex.org/W2083123353","https://openalex.org/W2110514755","https://openalex.org/W2114772983","https://openalex.org/W2120785033","https://openalex.org/W2125653639","https://openalex.org/W2129701824","https://openalex.org/W2135685510","https://openalex.org/W2153227646","https://openalex.org/W2154462472","https://openalex.org/W2154940055","https://openalex.org/W2159696955","https://openalex.org/W4240309467"],"related_works":["https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W2808484818","https://openalex.org/W1574948540","https://openalex.org/W2204754129","https://openalex.org/W275424163","https://openalex.org/W2156641820","https://openalex.org/W1569711686"],"abstract_inverted_index":{"Modern":[0],"field":[1],"programmable":[2],"gate":[3],"arrays":[4],"(FPGAs)":[5],"with":[6,19],"heterogeneous":[7],"resources":[8],"are":[9,92,110],"partially":[10,41],"reconfigurable.":[11],"Existing":[12],"methods":[13],"of":[14,29,80],"reconfiguration-aware":[15],"floorplanning":[16,50],"have":[17],"limitations":[18],"regard":[20],"to":[21,94,112,157],"homogeneous":[22],"resources;":[23],"they":[24],"solve":[25],"only":[26],"a":[27,37,48,71,102],"part":[28],"the":[30,55,68,78,81,99,114,118,124,139,144,153,158],"reconfigurable":[31,42,115],"problem.":[32],"In":[33,54,67,98,135],"this":[34],"paper,":[35],"first,":[36],"precise":[38],"model":[39],"for":[40],"FPGAs":[43],"is":[44,52,60,75,106,127],"formulated,":[45],"and":[46,87,108,129,131,147],"then,":[47],"two-phase":[49],"approach":[51,126],"presented.":[53],"proposed":[56,125],"approach,":[57],"resource":[58,96],"distribution":[59],"taken":[61],"into":[62],"consideration":[63],"at":[64],"all":[65],"times.":[66],"first":[69,145],"step,":[70,101,146],"resource-aware":[72,88,103],"insertion-after-remove":[73],"perturbation":[74],"devised":[76],"on":[77,117,150],"basis":[79],"multi-layer":[82],"sequence":[83],"pair":[84],"constraint":[85],"graphs,":[86],"slack-based":[89],"moves":[90],"(RASBM)":[91],"made":[93],"satisfy":[95],"requirements.":[97],"second":[100,154],"fixed-outline":[104],"floorplanner":[105],"used,":[107],"RASBM":[109],"applied":[111],"pack":[113],"regions":[116],"FPGAs.":[119],"Experimental":[120],"results":[121],"show":[122],"that":[123],"resource-":[128],"reconfiguration-aware,":[130],"facilitates":[132],"stable":[133],"floorplanning.":[134],"addition,":[136],"it":[137],"reduces":[138],"wire-length":[140,159],"by":[141,148],"4-28%":[142],"in":[143,152,160],"12%":[149],"average":[151],"step":[155],"compared":[156],"previous":[161],"approaches.":[162]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-09T07:52:08.696243","created_date":"2025-10-10T00:00:00"}
