{"id":"https://openalex.org/W2953786925","doi":"https://doi.org/10.1587/transele.2019ecs6003","title":"Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers","display_name":"Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers","publication_year":2019,"publication_date":"2019-06-24","ids":{"openalex":"https://openalex.org/W2953786925","doi":"https://doi.org/10.1587/transele.2019ecs6003","mag":"2953786925"},"language":"en","primary_location":{"id":"doi:10.1587/transele.2019ecs6003","is_oa":false,"landing_page_url":"https://doi.org/10.1587/transele.2019ecs6003","pdf_url":null,"source":{"id":"https://openalex.org/S2489501747","display_name":"IEICE Transactions on Electronics","issn_l":"0916-8524","issn":["0916-8524","1745-1353"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Electronics","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070962674","display_name":"Yongwoon Song","orcid":"https://orcid.org/0000-0003-4392-1603"},"institutions":[{"id":"https://openalex.org/I148751991","display_name":"Sogang University","ror":"https://ror.org/056tn4839","country_code":"KR","type":"education","lineage":["https://openalex.org/I148751991"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Yongwoon SONG","raw_affiliation_strings":["Sogang University"],"affiliations":[{"raw_affiliation_string":"Sogang University","institution_ids":["https://openalex.org/I148751991"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063170145","display_name":"Dongkeon Choi","orcid":null},"institutions":[{"id":"https://openalex.org/I148751991","display_name":"Sogang University","ror":"https://ror.org/056tn4839","country_code":"KR","type":"education","lineage":["https://openalex.org/I148751991"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dongkeon CHOI","raw_affiliation_strings":["Sogang University"],"affiliations":[{"raw_affiliation_string":"Sogang University","institution_ids":["https://openalex.org/I148751991"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001698754","display_name":"Hyuk\u2010Jun Lee","orcid":"https://orcid.org/0000-0003-2981-0800"},"institutions":[{"id":"https://openalex.org/I148751991","display_name":"Sogang University","ror":"https://ror.org/056tn4839","country_code":"KR","type":"education","lineage":["https://openalex.org/I148751991"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyukjun LEE","raw_affiliation_strings":["Sogang University"],"affiliations":[{"raw_affiliation_string":"Sogang University","institution_ids":["https://openalex.org/I148751991"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5070962674"],"corresponding_institution_ids":["https://openalex.org/I148751991"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.07991414,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"E102.C","issue":"12","first_page":"849","last_page":"852"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.703721284866333},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6839016675949097},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.6514648795127869},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6494220495223999},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.6257943511009216},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6056050062179565},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.600104570388794},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5732424259185791},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.5293757915496826},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4286649823188782},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42263099551200867},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.42250651121139526},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2851989269256592},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.27794069051742554},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.15075749158859253}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.703721284866333},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6839016675949097},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.6514648795127869},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6494220495223999},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.6257943511009216},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6056050062179565},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.600104570388794},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5732424259185791},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.5293757915496826},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4286649823188782},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42263099551200867},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.42250651121139526},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2851989269256592},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.27794069051742554},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.15075749158859253}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/transele.2019ecs6003","is_oa":false,"landing_page_url":"https://doi.org/10.1587/transele.2019ecs6003","pdf_url":null,"source":{"id":"https://openalex.org/S2489501747","display_name":"IEICE Transactions on Electronics","issn_l":"0916-8524","issn":["0916-8524","1745-1353"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Transactions on Electronics","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7599999904632568,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2071469142","https://openalex.org/W2101001844","https://openalex.org/W2101349595","https://openalex.org/W2105673382","https://openalex.org/W2162639668"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2185658074","https://openalex.org/W4285245242","https://openalex.org/W1725472669","https://openalex.org/W4243618206","https://openalex.org/W2019238062","https://openalex.org/W2138825797","https://openalex.org/W2896161911","https://openalex.org/W3049130895","https://openalex.org/W1707075782"],"abstract_inverted_index":{"The":[0,20,105,158],"performance":[1,21,70],"of":[2,22,41,146,155,182],"a":[3,23,42,45,101,177],"network":[4],"router/switch":[5],"has":[6],"improved":[7,84],"significantly":[8],"over":[9,171],"past":[10],"decades":[11],"with":[12],"explosively":[13],"increasing":[14,63],"internet":[15],"and":[16,52,57,65,138,153],"data":[17],"center":[18],"traffic.":[19],"router":[24],"heavily":[25],"depends":[26],"on":[27],"the":[28,39,69,96,134,172,183],"memory":[29,49,53,74,85,97,184],"system,":[30],"e.g.":[31],"DRAM":[32,147,156],"based":[33],"packet":[34,103,136],"buffers,":[35],"which":[36],"often":[37],"limits":[38],"scalability":[40],"router.":[43],"However,":[44],"widening":[46],"gap":[47],"between":[48],"I/O":[50],"bus":[51],"cell":[54],"array":[55],"speed":[56],"decreasing":[58],"row":[59,124,143],"buffer":[60,137,144],"locality":[61,145,152],"from":[62,72,121],"channels":[64],"banks":[66],"severely":[67],"reduce":[68],"gain":[71],"state-of-the-art":[73],"technology":[75],"such":[76],"as":[77],"DDR4":[78],"or":[79,91],"HBM2":[80],"DRAM.":[81],"Prior":[82],"works":[83],"bandwidth":[86,185],"by":[87],"maintaining":[88],"SRAM-based":[89],"per-queue":[90],"per-bank":[92],"input/output":[93],"buffers":[94,106],"in":[95,180],"controller":[98],"to":[99,117],"support":[100],"DRAM-based":[102,135],"buffer.":[104],"temporarily":[107],"store":[108],"packets":[109,141],"when":[110],"bank":[111],"conflicts":[112],"occur":[113],"but":[114],"are":[115],"unable":[116],"prevent":[118],"interference-inducing":[119],"traffic":[120],"thrashing":[122],"DRAM's":[123],"buffers.":[125],"In":[126],"this":[127],"study,":[128],"we":[129],"directly":[130],"integrate":[131],"SRAM":[132],"into":[133,148],"map":[139],"those":[140],"degrading":[142],"SRAM.":[149],"This":[150],"maximizes":[151],"parallelism":[154],"accesses.":[157],"proposed":[159],"scheme":[160,175],"can":[161],"benefit":[162],"any":[163],"existing":[164,174],"schemes.":[165],"Experimental":[166],"results":[167],"show":[168],"22.41%":[169],"improvement":[170],"best":[173],"for":[176],"single":[178],"channel":[179],"terms":[181],"utilization":[186],"under":[187],"harsh":[188],"congested":[189],"scenarios.":[190]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}