{"id":"https://openalex.org/W2991516383","doi":"https://doi.org/10.1587/elex.16.20190610","title":"A SLM-based overlay architecture for fine-grained virtual FPGA","display_name":"A SLM-based overlay architecture for fine-grained virtual FPGA","publication_year":2019,"publication_date":"2019-01-01","ids":{"openalex":"https://openalex.org/W2991516383","doi":"https://doi.org/10.1587/elex.16.20190610","mag":"2991516383"},"language":"en","primary_location":{"id":"doi:10.1587/elex.16.20190610","is_oa":true,"landing_page_url":"http://doi.org/10.1587/elex.16.20190610","pdf_url":"https://www.jstage.jst.go.jp/article/elex/16/24/16_16.20190610/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/elex/16/24/16_16.20190610/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035859063","display_name":"Theingi Myint","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Theingi Myint","raw_affiliation_strings":["Dept. of Computer Science and Electrical Engineering, Kumamoto University","Dept. of Computer Science and Electrical Engineering, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Electrical Engineering, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]},{"raw_affiliation_string":"Dept. of Computer Science and Electrical Engineering, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012465812","display_name":"Motoki Amagasaki","orcid":"https://orcid.org/0000-0002-5196-9765"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Motoki Amagasaki","raw_affiliation_strings":["Dept. of Computer Science and Electrical Engineering, Kumamoto University","Dept. of Computer Science and Electrical Engineering, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Electrical Engineering, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]},{"raw_affiliation_string":"Dept. of Computer Science and Electrical Engineering, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051831948","display_name":"Qian Zhao","orcid":"https://orcid.org/0000-0003-0032-1974"},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Qian Zhao","raw_affiliation_strings":["Kyushu Institute of Technology","Kyushu Institute of Technology, 680-4 Kawazu, Iizuka-shi, Fukuoka 820-8502, Japan"],"affiliations":[{"raw_affiliation_string":"Kyushu Institute of Technology","institution_ids":["https://openalex.org/I207014233"]},{"raw_affiliation_string":"Kyushu Institute of Technology, 680-4 Kawazu, Iizuka-shi, Fukuoka 820-8502, Japan","institution_ids":["https://openalex.org/I207014233"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059705629","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9654-2319"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Iida","raw_affiliation_strings":["Dept. of Computer Science and Electrical Engineering, Kumamoto University","Dept. of Computer Science and Electrical Engineering, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Electrical Engineering, Kumamoto University","institution_ids":["https://openalex.org/I96036126"]},{"raw_affiliation_string":"Dept. of Computer Science and Electrical Engineering, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5035859063"],"corresponding_institution_ids":["https://openalex.org/I96036126"],"apc_list":null,"apc_paid":null,"fwci":0.1769,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56048776,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"16","issue":"24","first_page":"20190610","last_page":"20190610"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9930999875068665,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8236232995986938},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.7446490526199341},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6835764646530151},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6234075427055359},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6226869821548462},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5686492919921875},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4342668056488037},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22296208143234253}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8236232995986938},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.7446490526199341},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6835764646530151},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6234075427055359},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6226869821548462},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5686492919921875},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4342668056488037},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22296208143234253},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/elex.16.20190610","is_oa":true,"landing_page_url":"http://doi.org/10.1587/elex.16.20190610","pdf_url":"https://www.jstage.jst.go.jp/article/elex/16/24/16_16.20190610/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/elex.16.20190610","is_oa":true,"landing_page_url":"http://doi.org/10.1587/elex.16.20190610","pdf_url":"https://www.jstage.jst.go.jp/article/elex/16/24/16_16.20190610/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2991516383.pdf","grobid_xml":"https://content.openalex.org/works/W2991516383.grobid-xml"},"referenced_works_count":34,"referenced_works":["https://openalex.org/W17851263","https://openalex.org/W1972387588","https://openalex.org/W1998922872","https://openalex.org/W2003820904","https://openalex.org/W2005602803","https://openalex.org/W2009950553","https://openalex.org/W2018873598","https://openalex.org/W2027103958","https://openalex.org/W2043542037","https://openalex.org/W2043574880","https://openalex.org/W2054951389","https://openalex.org/W2060519984","https://openalex.org/W2078444978","https://openalex.org/W2091330445","https://openalex.org/W2093426958","https://openalex.org/W2105011467","https://openalex.org/W2107350738","https://openalex.org/W2113263062","https://openalex.org/W2113645429","https://openalex.org/W2139637699","https://openalex.org/W2150022482","https://openalex.org/W2462602312","https://openalex.org/W2472489786","https://openalex.org/W2473515899","https://openalex.org/W2473737183","https://openalex.org/W2524721836","https://openalex.org/W2559278389","https://openalex.org/W2593661896","https://openalex.org/W2621788798","https://openalex.org/W2807281109","https://openalex.org/W4206262605","https://openalex.org/W4241238426","https://openalex.org/W4248265791","https://openalex.org/W4255745893"],"related_works":["https://openalex.org/W595346907","https://openalex.org/W153296825","https://openalex.org/W598989511","https://openalex.org/W2375779923","https://openalex.org/W1967800214","https://openalex.org/W2055675609","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2160474882"],"abstract_inverted_index":{"FPGA":[0,14,106],"overlay":[1,37],"technologies":[2],"have":[3,24],"been":[4],"introduced":[5],"to":[6,83,110],"provide":[7],"inter-FPGA":[8],"bitstream":[9],"compatibility":[10],"by":[11,81],"implementing":[12],"virtual":[13],"(vFPGA)":[15],"layers":[16],"on":[17,87,94,102],"physical":[18],"devices.":[19],"Conventional":[20],"LUT-based":[21,112],"finegrained":[22],"vFPGAs":[23],"very":[25],"large":[26],"resource":[27,79],"overheads.":[28],"In":[29],"this":[30],"paper,":[31],"we":[32],"propose":[33],"a":[34,49,70,95,103,111],"fine-grained":[35],"vFPGA":[36,73,113],"architecture":[38],"that":[39,69],"employs":[40],"our":[41],"previously":[42],"proposed":[43],"scalable":[44],"logic":[45,50],"module":[46],"(SLM)":[47],"as":[48,108],"cell.":[51],"SLMs":[52],"can":[53,74],"cover":[54],"most":[55],"frequently":[56],"used":[57],"logics":[58],"with":[59],"far":[60],"fewer":[61],"hardware":[62],"resources":[63],"than":[64],"LUTs.":[65],"Evaluation":[66],"results":[67],"show":[68],"7-input":[71],"SLM-based":[72],"reduce":[75],"LUT":[76],"and":[77,85,92,98,100],"flip-flop":[78],"usage":[80],"up":[82],"32%":[84],"35%":[86,93,101],"an":[88],"Artix-7":[89],"FPGA,":[90,97],"30%":[91,99],"Kintex-7":[96],"Kintex":[104],"UltraScale+":[105],"respectively,":[107],"compared":[109],"of":[114],"the":[115],"same":[116],"input":[117],"size.":[118]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}