{"id":"https://openalex.org/W2901901522","doi":"https://doi.org/10.1587/elex.15.20180943","title":"A SA-based parallel method for FPGA placement","display_name":"A SA-based parallel method for FPGA placement","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2901901522","doi":"https://doi.org/10.1587/elex.15.20180943","mag":"2901901522"},"language":"en","primary_location":{"id":"doi:10.1587/elex.15.20180943","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.15.20180943","pdf_url":"https://www.jstage.jst.go.jp/article/elex/15/24/15_15.20180943/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/elex/15/24/15_15.20180943/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014548453","display_name":"Chengyu Hu","orcid":"https://orcid.org/0000-0001-8226-5747"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chengyu Hu","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025981776","display_name":"Peng Lu","orcid":"https://orcid.org/0000-0003-0743-1068"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Peng Lu","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005595160","display_name":"Meng Yang","orcid":"https://orcid.org/0000-0003-2862-2015"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Meng Yang","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002847404","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0003-4361-8946"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.1263,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.49202722,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"15","issue":"24","first_page":"20180943","last_page":"20180943"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7905568480491638},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.77435302734375},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.765865683555603},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.6762798428535461},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.651194155216217},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.5342152714729309},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.5101040005683899},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.31103622913360596},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2012377381324768},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.08410915732383728},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.0699043869972229},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.05901739001274109}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7905568480491638},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.77435302734375},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.765865683555603},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.6762798428535461},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.651194155216217},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.5342152714729309},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.5101040005683899},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.31103622913360596},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2012377381324768},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.08410915732383728},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.0699043869972229},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.05901739001274109}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/elex.15.20180943","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.15.20180943","pdf_url":"https://www.jstage.jst.go.jp/article/elex/15/24/15_15.20180943/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/elex.15.20180943","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.15.20180943","pdf_url":"https://www.jstage.jst.go.jp/article/elex/15/24/15_15.20180943/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2901901522.pdf"},"referenced_works_count":11,"referenced_works":["https://openalex.org/W2005602803","https://openalex.org/W2007015871","https://openalex.org/W2023462222","https://openalex.org/W2024060531","https://openalex.org/W2064997970","https://openalex.org/W2071242375","https://openalex.org/W2114820519","https://openalex.org/W2164340799","https://openalex.org/W2773785779","https://openalex.org/W2886092906","https://openalex.org/W4243050516"],"related_works":["https://openalex.org/W2138311189","https://openalex.org/W3183044703","https://openalex.org/W2471703348","https://openalex.org/W1968931833","https://openalex.org/W1875577501","https://openalex.org/W2122425352","https://openalex.org/W108855261","https://openalex.org/W2098132017","https://openalex.org/W4244167835","https://openalex.org/W2031837447"],"abstract_inverted_index":{"In":[0,81],"this":[1],"paper,":[2],"we":[3],"present":[4],"a":[5,82,85],"serially-equivalent":[6],"parallel":[7,59,106],"method":[8,14,70],"to":[9,37,49,63,99],"accelerate":[10],"FPGA":[11,79],"placement.":[12],"Our":[13,69],"is":[15,47,61,71,91],"based":[16],"on":[17,29,93],"Simulated":[18],"Annealing":[19],"(SA)":[20],"Algorithm:":[21],"moves":[22],"of":[23,43,67,87,104],"placement":[24,75,102],"blocks":[25],"are":[26,34,108],"processed":[27],"concurrently":[28],"multiple":[30],"threads.":[31,97],"Two":[32],"strategies":[33],"adopted":[35],"here":[36],"guarantee":[38],"serial":[39,100],"equivalency:":[40],"task":[41],"switch":[42],"the":[44],"master":[45],"thread":[46],"used":[48],"handle":[50],"data":[51],"conflicts":[52],"aroused":[53],"by":[54,73],"parallel;":[55],"an":[56],"efficient":[57],"SA-based":[58],"framework":[60],"designed":[62],"obtain":[64],"orderly":[65],"flow":[66],"data.":[68],"tested":[72],"doing":[74],"for":[76],"Xilinx":[77],"xc4vlx200":[78],"chip.":[80],"quad-core":[83],"processor,":[84],"speedup":[86],"1.8\u00d7,":[88],"2.7\u00d7,":[89],"3.4\u00d7":[90],"achieved":[92],"2,":[94],"3,":[95],"4":[96],"Compared":[98],"placer,":[101],"results":[103],"our":[105],"placer":[107],"deterministic":[109],"and":[110],"have":[111],"no":[112],"quality":[113],"loss.":[114]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-05-22T06:13:13.366637","created_date":"2025-10-10T00:00:00"}
