{"id":"https://openalex.org/W2604902397","doi":"https://doi.org/10.1587/elex.14.20170218","title":"SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor","display_name":"SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor","publication_year":2017,"publication_date":"2017-01-01","ids":{"openalex":"https://openalex.org/W2604902397","doi":"https://doi.org/10.1587/elex.14.20170218","mag":"2604902397"},"language":"en","primary_location":{"id":"doi:10.1587/elex.14.20170218","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.14.20170218","pdf_url":"https://www.jstage.jst.go.jp/article/elex/14/8/14_14.20170218/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/elex/14/8/14_14.20170218/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100717935","display_name":"\u03a4ao Zhu","orcid":"https://orcid.org/0000-0003-0228-3916"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Taotao Zhu","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046536624","display_name":"Xiaoyan Xiang","orcid":"https://orcid.org/0000-0002-5602-2749"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyan Xiang","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100418370","display_name":"Chen Chen","orcid":"https://orcid.org/0000-0001-7587-3314"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chen Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022767878","display_name":"Jianyi Meng","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianyi Meng","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100717935"],"corresponding_institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":0.1461,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.48858011,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"14","issue":"8","first_page":"20170218","last_page":"20170218"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7193383574485779},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6992824673652649},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6096864342689514},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.6050223708152771},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.47092312574386597},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.47074398398399353},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.44569021463394165},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.42572855949401855},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4125024378299713},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36911362409591675},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.22308123111724854},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17623576521873474},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.16699448227882385},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15546822547912598},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13790056109428406}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7193383574485779},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6992824673652649},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6096864342689514},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.6050223708152771},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.47092312574386597},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.47074398398399353},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.44569021463394165},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.42572855949401855},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4125024378299713},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36911362409591675},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.22308123111724854},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17623576521873474},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.16699448227882385},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15546822547912598},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13790056109428406},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/elex.14.20170218","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.14.20170218","pdf_url":"https://www.jstage.jst.go.jp/article/elex/14/8/14_14.20170218/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/elex.14.20170218","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.14.20170218","pdf_url":"https://www.jstage.jst.go.jp/article/elex/14/8/14_14.20170218/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G1014697965","display_name":null,"funder_award_id":"15ZR1402700","funder_id":"https://openalex.org/F4320321885","funder_display_name":"Science and Technology Commission of Shanghai Municipality"},{"id":"https://openalex.org/G3398006070","display_name":null,"funder_award_id":"2015AA016601","funder_id":"https://openalex.org/F4320321540","funder_display_name":"Ministry of Science and Technology of the People's Republic of China"}],"funders":[{"id":"https://openalex.org/F4320321540","display_name":"Ministry of Science and Technology of the People's Republic of China","ror":"https://ror.org/027s68j25"},{"id":"https://openalex.org/F4320321885","display_name":"Science and Technology Commission of Shanghai Municipality","ror":"https://ror.org/03kt66j61"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2604902397.pdf","grobid_xml":"https://content.openalex.org/works/W2604902397.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W2035342163","https://openalex.org/W2048719801","https://openalex.org/W2082597509","https://openalex.org/W2095351656","https://openalex.org/W2106648230","https://openalex.org/W2113682107","https://openalex.org/W2124002183","https://openalex.org/W2156667996","https://openalex.org/W2178304595","https://openalex.org/W2289333215","https://openalex.org/W2319322381","https://openalex.org/W3141370589"],"related_works":["https://openalex.org/W1968053645","https://openalex.org/W3152276953","https://openalex.org/W1969440359","https://openalex.org/W2046086627","https://openalex.org/W2161460378","https://openalex.org/W2183693050","https://openalex.org/W2783673891","https://openalex.org/W2526933509","https://openalex.org/W2803734506","https://openalex.org/W2999612013"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,35],"self-gated":[4],"error":[5,30,45,63,82],"resilient":[6,31],"cluster":[7],"of":[8,43],"sequential":[9],"cells":[10],"(SGERC)":[11],"to":[12,29,79],"sample":[13],"the":[14,41,54,61,74,97,103],"critical":[15,69],"data":[16],"in":[17],"wide-voltage":[18],"operation":[19],"for":[20,53],"EDAC":[21,105],"system.":[22],"SGERC":[23,88],"introduces":[24],"latch-based":[25],"clock":[26,37,76],"gating":[27,77],"technique":[28],"circuits":[32,65,78],"and":[33,72,100],"proposes":[34],"customized":[36],"gate":[38],"which":[39],"has":[40],"ability":[42],"timing":[44,62,81],"self-correction":[46],"with":[47,96],"only":[48],"two":[49],"additional":[50],"transistors":[51],"added":[52],"first":[55],"time.":[56],"Further,":[57],"it":[58],"totally":[59],"eliminates":[60],"detection":[64],"required":[66],"by":[67],"each":[68],"register":[70],"before":[71],"utilizes":[73],"data-driven":[75],"generate":[80],"information.":[83],"Simulation":[84],"results":[85],"show":[86],"that":[87],"design":[89,99],"achieves":[90],"58.3%":[91],"energy":[92],"efficiency":[93],"improvement":[94],"compared":[95],"baseline":[98],"19.4%":[101],"over":[102],"latest":[104],"design.":[106]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}
