{"id":"https://openalex.org/W2508705699","doi":"https://doi.org/10.1587/elex.13.20160676","title":"Prototyping design of a flexible DSP block with pipeline structure for FPGA","display_name":"Prototyping design of a flexible DSP block with pipeline structure for FPGA","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2508705699","doi":"https://doi.org/10.1587/elex.13.20160676","mag":"2508705699"},"language":"en","primary_location":{"id":"doi:10.1587/elex.13.20160676","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.13.20160676","pdf_url":"https://www.jstage.jst.go.jp/article/elex/13/17/13_13.20160676/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/elex/13/17/13_13.20160676/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078385434","display_name":"Hanyang Xu","orcid":"https://orcid.org/0009-0000-0328-9610"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hanyang Xu","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002847404","display_name":"Jian Wang","orcid":"https://orcid.org/0000-0003-4361-8946"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Wang","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081419061","display_name":"Jinmei Lai","orcid":"https://orcid.org/0009-0003-5238-4720"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinmei Lai","raw_affiliation_strings":["ASIC and System State Key Laboratory, Fudan University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASIC and System State Key Laboratory, Fudan University","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.08292683,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"13","issue":"17","first_page":"20160676","last_page":"20160676"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8078103065490723},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7816630005836487},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.7368466854095459},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6669065952301025},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6613826751708984},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5491788387298584},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5040847063064575},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.48895251750946045},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4642999768257141},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15368369221687317},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.05627483129501343}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8078103065490723},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7816630005836487},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7368466854095459},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6669065952301025},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6613826751708984},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5491788387298584},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5040847063064575},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.48895251750946045},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4642999768257141},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15368369221687317},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.05627483129501343},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/elex.13.20160676","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.13.20160676","pdf_url":"https://www.jstage.jst.go.jp/article/elex/13/17/13_13.20160676/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/elex.13.20160676","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.13.20160676","pdf_url":"https://www.jstage.jst.go.jp/article/elex/13/17/13_13.20160676/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321851","display_name":"Fudan University","ror":"https://ror.org/013q1eq08"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2508705699.pdf","grobid_xml":"https://content.openalex.org/works/W2508705699.grobid-xml"},"referenced_works_count":13,"referenced_works":["https://openalex.org/W1535148441","https://openalex.org/W1557130217","https://openalex.org/W1963965124","https://openalex.org/W2004940452","https://openalex.org/W2012606349","https://openalex.org/W2108351048","https://openalex.org/W2113724275","https://openalex.org/W2117146383","https://openalex.org/W2118340347","https://openalex.org/W2143803406","https://openalex.org/W2160263582","https://openalex.org/W2168543008","https://openalex.org/W4206262605"],"related_works":["https://openalex.org/W1876592433","https://openalex.org/W2998132311","https://openalex.org/W2083269738","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W1692883217","https://openalex.org/W2406926880","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W2291257309"],"abstract_inverted_index":{"Embedded":[0],"hard":[1],"DSP":[2,16,26,42,83],"block":[3,43,84],"effectively":[4],"improves":[5],"FPGA":[6],"performance":[7],"for":[8],"arithmetic":[9],"circuits.":[10],"This":[11,39],"paper":[12],"proposes":[13],"a":[14,20,48,74,97],"novel":[15],"architecture.":[17],"By":[18],"adopting":[19],"new":[21],"Compressor":[22,79,109],"Array,":[23],"the":[24,41,68,78,106],"proposed":[25,82],"can":[27],"additionally":[28],"supports":[29],"multi-operand":[30,55],"addition":[31,56],"which":[32],"current":[33],"commercial":[34],"devices":[35],"do":[36],"not":[37],"support.":[38],"makes":[40],"more":[44,69],"versatile":[45],"to":[46,105],"cover":[47],"wider":[49],"range":[50],"of":[51],"applications.":[52],"But":[53],"supporting":[54],"will":[57],"significantly":[58],"increase":[59],"routing":[60],"congestion.":[61],"To":[62],"alleviate":[63],"timing":[64],"degeneration":[65],"caused":[66],"by":[67],"congestion":[70],"routing,":[71],"we":[72],"implement":[73],"pipelined":[75],"design":[76],"in":[77,87,100],"Array.":[80],"The":[81],"is":[85],"fabricated":[86],"1P10M":[88],"65":[89],"nm":[90],"bulk":[91],"CMOS":[92],"process,":[93],"Test":[94],"results":[95],"show":[96],"53.7%":[98],"reduction":[99],"critical":[101],"path":[102],"delay":[103],"compared":[104],"Field":[107],"Programmable":[108],"Tree":[110],"(FPCT).":[111]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-08-06T08:24:18.245995","created_date":"2025-10-10T00:00:00"}
