{"id":"https://openalex.org/W1978398424","doi":"https://doi.org/10.1587/elex.12.20150115","title":"PCRAM-aware cluster allocation algorithm for hybrid main memory hierarchy","display_name":"PCRAM-aware cluster allocation algorithm for hybrid main memory hierarchy","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W1978398424","doi":"https://doi.org/10.1587/elex.12.20150115","mag":"1978398424"},"language":"en","primary_location":{"id":"doi:10.1587/elex.12.20150115","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.12.20150115","pdf_url":"https://www.jstage.jst.go.jp/article/elex/12/5/12_12.20150115/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.jstage.jst.go.jp/article/elex/12/5/12_12.20150115/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037941517","display_name":"Shunfen Li","orcid":"https://orcid.org/0000-0002-2464-1414"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210147322","display_name":"Shanghai Institute of Microsystem and Information Technology","ror":"https://ror.org/04nytyj38","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210147322"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shunfen Li","raw_affiliation_strings":["State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences","institution_ids":["https://openalex.org/I4210147322","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100764041","display_name":"Xiao-Gang Chen","orcid":"https://orcid.org/0000-0003-4508-3391"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210147322","display_name":"Shanghai Institute of Microsystem and Information Technology","ror":"https://ror.org/04nytyj38","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210147322"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaogang Chen","raw_affiliation_strings":["State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences","institution_ids":["https://openalex.org/I4210147322","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100946469","display_name":"Mi Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210147322","display_name":"Shanghai Institute of Microsystem and Information Technology","ror":"https://ror.org/04nytyj38","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210147322"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mi Zhou","raw_affiliation_strings":["State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences","institution_ids":["https://openalex.org/I4210147322","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009211176","display_name":"Gezi Li","orcid":"https://orcid.org/0000-0002-4101-1043"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210147322","display_name":"Shanghai Institute of Microsystem and Information Technology","ror":"https://ror.org/04nytyj38","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210147322"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Gezi Li","raw_affiliation_strings":["State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences","institution_ids":["https://openalex.org/I4210147322","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040322824","display_name":"Yiyun Zhang","orcid":"https://orcid.org/0000-0002-1419-485X"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210147322","display_name":"Shanghai Institute of Microsystem and Information Technology","ror":"https://ror.org/04nytyj38","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210147322"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yiyun Zhang","raw_affiliation_strings":["State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences","institution_ids":["https://openalex.org/I4210147322","https://openalex.org/I19820366"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100366515","display_name":"Zhitang Song","orcid":"https://orcid.org/0000-0001-7859-9429"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210147322","display_name":"Shanghai Institute of Microsystem and Information Technology","ror":"https://ror.org/04nytyj38","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210147322"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhitang Song","raw_affiliation_strings":["State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences","institution_ids":["https://openalex.org/I4210147322","https://openalex.org/I19820366"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3507,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.66252041,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"12","issue":"5","first_page":"20150115","last_page":"20150115"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7817785739898682},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5998507738113403},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5858107805252075},{"id":"https://openalex.org/keywords/write-buffer","display_name":"Write buffer","score":0.577660083770752},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.569994330406189},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.5683739185333252},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.5595709085464478},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.549135148525238},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.45095813274383545},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.443086177110672},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4294319450855255},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35858139395713806},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3523225784301758},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3395138382911682},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.33493900299072266},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.27385175228118896},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1585426926612854},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09198397397994995},{"id":"https://openalex.org/keywords/phase-change","display_name":"Phase change","score":0.08805575966835022},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.0762782096862793},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06661707162857056}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7817785739898682},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5998507738113403},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5858107805252075},{"id":"https://openalex.org/C89089495","wikidata":"https://www.wikidata.org/wiki/Q8038418","display_name":"Write buffer","level":5,"score":0.577660083770752},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.569994330406189},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.5683739185333252},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.5595709085464478},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.549135148525238},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.45095813274383545},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.443086177110672},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4294319450855255},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35858139395713806},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3523225784301758},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3395138382911682},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.33493900299072266},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.27385175228118896},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1585426926612854},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09198397397994995},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.08805575966835022},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.0762782096862793},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06661707162857056},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.0},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/elex.12.20150115","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.12.20150115","pdf_url":"https://www.jstage.jst.go.jp/article/elex/12/5/12_12.20150115/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/elex.12.20150115","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.12.20150115","pdf_url":"https://www.jstage.jst.go.jp/article/elex/12/5/12_12.20150115/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":true,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1978398424.pdf","grobid_xml":"https://content.openalex.org/works/W1978398424.grobid-xml"},"referenced_works_count":7,"referenced_works":["https://openalex.org/W2021376332","https://openalex.org/W2028802049","https://openalex.org/W2124306283","https://openalex.org/W2125812397","https://openalex.org/W2146245483","https://openalex.org/W2169863928","https://openalex.org/W2917663763"],"related_works":["https://openalex.org/W2999811406","https://openalex.org/W2561145363","https://openalex.org/W4386903460","https://openalex.org/W2028802049","https://openalex.org/W2924367614","https://openalex.org/W1978051091","https://openalex.org/W2053735247","https://openalex.org/W4256048894","https://openalex.org/W2178010602","https://openalex.org/W2126830366"],"abstract_inverted_index":{"Phase":[0],"Change":[1],"Random":[2],"Access":[3],"Memory":[4],"(PCRAM)":[5],"has":[6],"several":[7],"characteristics":[8],"that":[9,83],"make":[10],"it":[11],"a":[12,38,58],"promising":[13],"candidate":[14],"for":[15,47,62],"main":[16,29],"memory.":[17],"In":[18],"this":[19],"paper,":[20],"the":[21,28,53,63,84,90,99,103],"challenges":[22],"involved":[23],"in":[24],"incorporating":[25],"PCRAM":[26,44],"into":[27],"memory":[30,40,65],"hierarchy":[31,41],"of":[32,43,56,76,92,98],"flash-based":[33],"systems":[34],"are":[35],"explored,":[36],"and":[37,45,95,101],"hybrid":[39,64],"consisting":[42],"DRAM":[46],"SSD":[48,100],"is":[49,66,72],"proposed.":[50],"To":[51],"reduce":[52],"write":[54,94],"traffic":[55],"Flash,":[57],"buffer":[59,86],"management":[60],"scheme":[61,70],"implemented.":[67],"The":[68,79],"proposed":[69,85],"above":[71],"implemented":[73],"on":[74],"basis":[75],"Disksim":[77],"platform.":[78],"simulation":[80],"results":[81],"indicate":[82],"algorithm":[87],"can":[88],"decrease":[89],"number":[91],"random":[93],"erase":[96],"operations":[97],"improve":[102],"average":[104],"system":[105],"response":[106],"rate":[107],"obviously.":[108]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}