{"id":"https://openalex.org/W2060219035","doi":"https://doi.org/10.1587/elex.10.20130887","title":"On-chip long-term jitter measurement for PLL based on undersampling technique","display_name":"On-chip long-term jitter measurement for PLL based on undersampling technique","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W2060219035","doi":"https://doi.org/10.1587/elex.10.20130887","mag":"2060219035"},"language":"en","primary_location":{"id":"doi:10.1587/elex.10.20130887","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.10.20130887","pdf_url":"https://www.jstage.jst.go.jp/article/elex/10/24/10_10.20130887/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://www.jstage.jst.go.jp/article/elex/10/24/10_10.20130887/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062180403","display_name":"Zhikuang Cai","orcid":"https://orcid.org/0000-0002-0264-3849"},"institutions":[{"id":"https://openalex.org/I4210090971","display_name":"Southeast University","ror":"https://ror.org/00cf0ab87","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210090971"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Zhikuang Cai","raw_affiliation_strings":["National ASIC System Engineering Research Center, Southeast University","National ASIC system Engineering Research Center, Southeast University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]},{"raw_affiliation_string":"National ASIC system Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049597899","display_name":"Haobo Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210090971","display_name":"Southeast University","ror":"https://ror.org/00cf0ab87","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210090971"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Haobo Xu","raw_affiliation_strings":["National ASIC System Engineering Research Center, Southeast University","National ASIC system Engineering Research Center, Southeast University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]},{"raw_affiliation_string":"National ASIC system Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078494266","display_name":"Shixuan Que","orcid":null},"institutions":[{"id":"https://openalex.org/I4210090971","display_name":"Southeast University","ror":"https://ror.org/00cf0ab87","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210090971"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Shixuan Que","raw_affiliation_strings":["National ASIC System Engineering Research Center, Southeast University","National ASIC system Engineering Research Center, Southeast University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]},{"raw_affiliation_string":"National ASIC system Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057291086","display_name":"Weiwei Shan","orcid":"https://orcid.org/0000-0001-5520-1326"},"institutions":[{"id":"https://openalex.org/I4210090971","display_name":"Southeast University","ror":"https://ror.org/00cf0ab87","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210090971"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Weiwei Shan","raw_affiliation_strings":["National ASIC System Engineering Research Center, Southeast University","National ASIC system Engineering Research Center, Southeast University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]},{"raw_affiliation_string":"National ASIC system Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030384645","display_name":"Jun Yang","orcid":"https://orcid.org/0000-0002-8379-0321"},"institutions":[{"id":"https://openalex.org/I4210090971","display_name":"Southeast University","ror":"https://ror.org/00cf0ab87","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210090971"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Jun Yang","raw_affiliation_strings":["National ASIC System Engineering Research Center, Southeast University","National ASIC system Engineering Research Center, Southeast University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]},{"raw_affiliation_string":"National ASIC system Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210090971"],"apc_list":null,"apc_paid":null,"fwci":0.2055,"has_fulltext":true,"cited_by_count":5,"citation_normalized_percentile":{"value":0.63026904,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"10","issue":"24","first_page":"20130887","last_page":"20130887"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/undersampling","display_name":"Undersampling","score":0.955549955368042},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9280056357383728},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7388807535171509},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5853559970855713},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5586044788360596},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5038630366325378},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5011734962463379},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46130993962287903},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4521290957927704},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18528017401695251},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10488930344581604}],"concepts":[{"id":"https://openalex.org/C136536468","wikidata":"https://www.wikidata.org/wiki/Q1225894","display_name":"Undersampling","level":2,"score":0.955549955368042},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9280056357383728},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7388807535171509},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5853559970855713},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5586044788360596},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5038630366325378},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5011734962463379},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46130993962287903},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4521290957927704},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18528017401695251},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10488930344581604},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/elex.10.20130887","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.10.20130887","pdf_url":"https://www.jstage.jst.go.jp/article/elex/10/24/10_10.20130887/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/elex.10.20130887","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.10.20130887","pdf_url":"https://www.jstage.jst.go.jp/article/elex/10/24/10_10.20130887/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G50917148","display_name":"\u6781\u4f4e\u529f\u8017SoC\u82af\u7247\u8d85\u7ea7\u52a8\u6001\u7535\u538b\u8c03\u8282\u5173\u952e\u6280\u672f\u7814\u7a76","funder_award_id":"61006029","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320323970","display_name":"Ministry of Industry and Information Technology of the People's Republic of China","ror":"https://ror.org/0385nmy68"}],"has_content":{"grobid_xml":false,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2060219035.pdf"},"referenced_works_count":10,"referenced_works":["https://openalex.org/W569179405","https://openalex.org/W2013669348","https://openalex.org/W2023148549","https://openalex.org/W2040717930","https://openalex.org/W2045718689","https://openalex.org/W2079687035","https://openalex.org/W2108636921","https://openalex.org/W2162231736","https://openalex.org/W2176875671","https://openalex.org/W3014608155"],"related_works":["https://openalex.org/W984417604","https://openalex.org/W2498262093","https://openalex.org/W2139484866","https://openalex.org/W2188779191","https://openalex.org/W2967785526","https://openalex.org/W188830667","https://openalex.org/W1605914315","https://openalex.org/W4360861688","https://openalex.org/W1977306627","https://openalex.org/W3134930219"],"abstract_inverted_index":{"An":[0],"all-digital":[1],"circuit":[2,23,81,107],"for":[3,67],"on-chip":[4],"measuring":[5,68],"the":[6,14,25,30,35,41,45,69,84,122],"long-term":[7,70,128],"jitter":[8,71,129],"of":[9,44,72,124,130],"Phase-Locked":[10],"Loop":[11],"(PLL)":[12],"using":[13],"undersampling":[15,26],"technique":[16],"is":[17,51,65,90,102],"presented":[18],"in":[19,110,114],"this":[20],"paper.":[21],"The":[22,47,76,106],"comprises":[24],"circuit,":[27,38],"which":[28,39,64],"samples":[29],"PLL":[31,73,85],"output":[32,86],"signal":[33,87],"and":[34,112],"data":[36,48,55],"analysis":[37],"calculates":[40],"statistical":[42],"value":[43],"jitter.":[46],"statistics":[49],"approach":[50],"based":[52],"on":[53],"accumulating":[54],"from":[56],"multiple":[57],"edge":[58,62],"regions":[59],"with":[60,134],"cycle":[61],"alignment,":[63],"suitable":[66],"clock":[74,133],"signal.":[75],"proposed":[77],"built-in":[78],"self-test":[79],"(BIST)":[80],"can":[82,96],"test":[83],"whose":[88],"frequency":[89],"greater":[91],"than":[92,136],"1GHz.":[93],"And":[94],"it":[95],"provide":[97],"high":[98],"measurement":[99],"resolution":[100],"that":[101],"up":[103],"to":[104],"1ps.":[105],"was":[108],"designed":[109],"Verilog,":[111],"fabricated":[113],"TSMC":[115],"130nm":[116],"CMOS":[117],"process.":[118],"Simulated":[119],"results":[120],"show":[121],"possibility":[123],"detecting":[125],"45ps":[126],"RMS":[127],"a":[131],"1GHz":[132],"less":[135],"2%":[137],"error.":[138]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-08-01T09:00:35.917206","created_date":"2025-10-10T00:00:00"}
