{"id":"https://openalex.org/W2069729666","doi":"https://doi.org/10.1587/elex.10.20130494","title":"A wide-range and ultra fast-locking all-digital SAR DLL without harmonic-locking","display_name":"A wide-range and ultra fast-locking all-digital SAR DLL without harmonic-locking","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W2069729666","doi":"https://doi.org/10.1587/elex.10.20130494","mag":"2069729666"},"language":"en","primary_location":{"id":"doi:10.1587/elex.10.20130494","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.10.20130494","pdf_url":"https://www.jstage.jst.go.jp/article/elex/10/22/10_10.20130494/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://www.jstage.jst.go.jp/article/elex/10/22/10_10.20130494/_pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062180403","display_name":"Zhikuang Cai","orcid":"https://orcid.org/0000-0002-0264-3849"},"institutions":[{"id":"https://openalex.org/I4210090971","display_name":"Southeast University","ror":"https://ror.org/00cf0ab87","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210090971"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Zhikuang Cai","raw_affiliation_strings":["National ASIC System Engineering Research Center, Southeast University","National ASIC system Engineering Research Center, Southeast University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]},{"raw_affiliation_string":"National ASIC system Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108575617","display_name":"Tailong Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I143868143","display_name":"Anhui University","ror":"https://ror.org/05th6yx34","country_code":"CN","type":"education","lineage":["https://openalex.org/I143868143"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tailong Xu","raw_affiliation_strings":["School of Electronics and Information, Anhui University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics and Information, Anhui University","institution_ids":["https://openalex.org/I143868143"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100359479","display_name":"Haiyan Sun","orcid":"https://orcid.org/0000-0001-5498-8251"},"institutions":[{"id":"https://openalex.org/I4210090971","display_name":"Southeast University","ror":"https://ror.org/00cf0ab87","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210090971"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Haiyan Sun","raw_affiliation_strings":["National ASIC System Engineering Research Center, Southeast University","National ASIC system Engineering Research Center, Southeast University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]},{"raw_affiliation_string":"National ASIC system Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101499715","display_name":"Longxing Shi","orcid":"https://orcid.org/0000-0002-0629-7154"},"institutions":[{"id":"https://openalex.org/I4210090971","display_name":"Southeast University","ror":"https://ror.org/00cf0ab87","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210090971"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Longxing Shi","raw_affiliation_strings":["National ASIC System Engineering Research Center, Southeast University","National ASIC system Engineering Research Center, Southeast University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC System Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]},{"raw_affiliation_string":"National ASIC system Engineering Research Center, Southeast University","institution_ids":["https://openalex.org/I4210090971"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.10116685,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"10","issue":"22","first_page":"20130494","last_page":"20130494"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6453041434288025},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5625463724136353},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.49575337767601013},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49525848031044006},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.47649043798446655},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.45752060413360596},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4510098397731781},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.37301313877105713},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.286176472902298},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20656374096870422},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.15431973338127136},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08254307508468628}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6453041434288025},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5625463724136353},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.49575337767601013},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49525848031044006},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.47649043798446655},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.45752060413360596},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4510098397731781},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.37301313877105713},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.286176472902298},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20656374096870422},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.15431973338127136},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08254307508468628},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1587/elex.10.20130494","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.10.20130494","pdf_url":"https://www.jstage.jst.go.jp/article/elex/10/22/10_10.20130494/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1587/elex.10.20130494","is_oa":true,"landing_page_url":"https://doi.org/10.1587/elex.10.20130494","pdf_url":"https://www.jstage.jst.go.jp/article/elex/10/22/10_10.20130494/_pdf","source":{"id":"https://openalex.org/S207433681","display_name":"IEICE Electronics Express","issn_l":"1349-2543","issn":["1349-2543","1349-9467"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEICE Electronics Express","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2069729666.pdf","grobid_xml":"https://content.openalex.org/works/W2069729666.grobid-xml"},"referenced_works_count":5,"referenced_works":["https://openalex.org/W2018092108","https://openalex.org/W2018623323","https://openalex.org/W2098302131","https://openalex.org/W2126227985","https://openalex.org/W2547031838"],"related_works":["https://openalex.org/W2354050524","https://openalex.org/W2083878249","https://openalex.org/W2401743820","https://openalex.org/W3177439118","https://openalex.org/W4295813049","https://openalex.org/W2119216036","https://openalex.org/W2389594899","https://openalex.org/W2976219355","https://openalex.org/W2900271051","https://openalex.org/W766471173"],"abstract_inverted_index":{"A":[0],"novel":[1],"implementation":[2],"of":[3,48],"the":[4,33,40,45,49,70],"complete":[5],"all-digital":[6],"M-b":[7],"successive":[8],"approximation":[9],"register-controlled":[10],"delay-locked":[11],"loop":[12],"(SAR":[13],"DLL)":[14],"is":[15],"presented":[16],"with":[17],"wide-range,":[18],"reduced":[19],"hardware":[20],"overhead":[21],"and":[22,43,64],"close":[23],"to":[24,38,67],"50%":[25],"duty":[26],"cycle.":[27],"The":[28],"proposed":[29],"SAR":[30,51],"DLL":[31],"adopts":[32],"digital-controlled":[34],"resettable":[35],"delay":[36],"line":[37],"achieve":[39],"ultra":[41],"fast-locking":[42],"eliminate":[44],"harmonic-locking":[46],"issue":[47],"conventional":[50],"ADDLL":[52],"in":[53,62],"wide-range":[54],"application.":[55],"All":[56],"design":[57],"units":[58],"are":[59],"first":[60],"described":[61],"verilog,":[63],"then":[65],"mapped":[66],"silicon":[68],"using":[69],"SMIC":[71],"0.18\u03bcm":[72],"CMOS":[73],"Artisan":[74],"standard":[75],"cell":[76],"library.":[77]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-08-01T09:00:35.917206","created_date":"2025-10-10T00:00:00"}