{"id":"https://openalex.org/W2000688841","doi":"https://doi.org/10.1504/ijes.2005.009956","title":"A system approach for partially reconfigurable architectures","display_name":"A system approach for partially reconfigurable architectures","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2000688841","doi":"https://doi.org/10.1504/ijes.2005.009956","mag":"2000688841"},"language":"en","primary_location":{"id":"doi:10.1504/ijes.2005.009956","is_oa":false,"landing_page_url":"https://doi.org/10.1504/ijes.2005.009956","pdf_url":null,"source":{"id":"https://openalex.org/S204369148","display_name":"International Journal of Embedded Systems","issn_l":"1741-1068","issn":["1741-1068","1741-1076"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310317825","host_organization_name":"Inderscience Publishers","host_organization_lineage":["https://openalex.org/P4310317825"],"host_organization_lineage_names":["Inderscience Publishers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Embedded Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030056981","display_name":"Heiko Kalte","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Heiko Kalte","raw_affiliation_strings":[""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019897299","display_name":"Boris Kettelhoit","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Boris Kettelhoit","raw_affiliation_strings":[""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041162707","display_name":"Markus Koester","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Markus Koester","raw_affiliation_strings":[""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028498307","display_name":"Mario Porrmann","orcid":"https://orcid.org/0000-0003-1005-5753"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mario Porrmann","raw_affiliation_strings":[""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043372144","display_name":"Ulrich R\u00fcckert","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ulrich Ruckert","raw_affiliation_strings":[""],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0561,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.78129185,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":"3/4","first_page":"274","last_page":"274"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8958349227905273},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8409296274185181},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7532495856285095},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.6258546710014343},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5312886834144592},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4873831868171692},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4356245994567871}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8958349227905273},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8409296274185181},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7532495856285095},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6258546710014343},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5312886834144592},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4873831868171692},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4356245994567871}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1504/ijes.2005.009956","is_oa":false,"landing_page_url":"https://doi.org/10.1504/ijes.2005.009956","pdf_url":null,"source":{"id":"https://openalex.org/S204369148","display_name":"International Journal of Embedded Systems","issn_l":"1741-1068","issn":["1741-1068","1741-1076"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310317825","host_organization_name":"Inderscience Publishers","host_organization_lineage":["https://openalex.org/P4310317825"],"host_organization_lineage_names":["Inderscience Publishers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Embedded Systems","raw_type":"journal-article"},{"id":"pmh:oai:pub.librecat.org:2285654","is_oa":false,"landing_page_url":"https://pub.uni-bielefeld.de/record/2285654","pdf_url":null,"source":{"id":"https://openalex.org/S4306401671","display_name":"PUB \u2013 Publications at Bielefeld University (Bielefeld University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I20121455","host_organization_name":"Bielefeld University","host_organization_lineage":["https://openalex.org/I20121455"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Kalte H, Kettelhoit B, Koester M, Porrmann M, R\u00fcckert U. A System Approach for Partially Reconfigurable Architectures. <em>International Journal of Embedded Systems (IJES), Inderscience Publisher</em>. 2005;1(3/4):274-290.","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6299999952316284,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2361654132","https://openalex.org/W2340647897","https://openalex.org/W2808484818","https://openalex.org/W1574948540","https://openalex.org/W2204754129","https://openalex.org/W275424163","https://openalex.org/W1569711686"],"abstract_inverted_index":{"The":[0],"increasing":[1],"logic":[2],"density":[3],"of":[4,14,23,30,71,93],"current":[5],"Field":[6],"Programmable":[7],"Gate":[8],"Arrays":[9],"(FPGA)":[10],"enables":[11],"the":[12,28,86,94],"integration":[13,49],"whole":[15],"systems":[16,32],"on":[17,50],"one":[18],"programmable":[19],"chip.":[20],"Using":[21],"concepts":[22],"partial":[24],"dynamic":[25,47],"reconfiguration":[26],"allows":[27,68],"adaptation":[29],"complex":[31],"to":[33,56],"changing":[34],"requirements":[35],"at":[36],"run-time.":[37],"In":[38,54],"this":[39],"paper":[40],"we":[41,83],"present":[42],"a":[43,77],"realisable":[44],"approach":[45,67],"for":[46,63],"system":[48],"Xilinx":[51],"Virtex":[52],"FPGAs.":[53],"contrast":[55],"existing":[57],"approaches":[58],"that":[59,85],"consider":[60],"fixed":[61],"slots":[62],"module":[64],"placement,":[65],"our":[66],"fine-grained":[69],"placement":[70],"modules":[72],"with":[73],"variable":[74],"width":[75],"along":[76],"horizontal":[78],"communication":[79],"infrastructure.":[80],"By":[81],"simulation":[82],"show":[84],"proposed":[87],"1D-approach":[88],"outperforms":[89],"2D-approaches":[90],"by":[91],"means":[92],"device":[95],"utilisation":[96],"and":[97],"external":[98],"fragmentation.":[99]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}