{"id":"https://openalex.org/W4232541186","doi":"https://doi.org/10.1504/ijhpcn.2019.097052","title":"Developments in memory management in OpenMP","display_name":"Developments in memory management in OpenMP","publication_year":2018,"publication_date":"2018-12-18","ids":{"openalex":"https://openalex.org/W4232541186","doi":"https://doi.org/10.1504/ijhpcn.2019.097052"},"language":"en","primary_location":{"id":"doi:10.1504/ijhpcn.2019.097052","is_oa":true,"landing_page_url":"https://doi.org/10.1504/ijhpcn.2019.097052","pdf_url":"https://doi.org/10.1504/ijhpcn.2019.097052","source":{"id":"https://openalex.org/S159903936","display_name":"International Journal of High Performance Computing and Networking","issn_l":"1740-0562","issn":["1740-0562","1740-0570"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310317825","host_organization_name":"Inderscience Publishers","host_organization_lineage":["https://openalex.org/P4310317825"],"host_organization_lineage_names":["Inderscience Publishers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of High Performance Computing and Networking","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://doi.org/10.1504/ijhpcn.2019.097052","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041290212","display_name":"Jason Sewall","orcid":"https://orcid.org/0000-0001-9482-3558"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210128612","display_name":"Mission College","ror":"https://ror.org/035fpgr29","country_code":"US","type":"education","lineage":["https://openalex.org/I4210128612"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason Sewall","raw_affiliation_strings":["Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210128612"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084262733","display_name":"S. J. Pennycook","orcid":"https://orcid.org/0000-0003-0237-3823"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210128612","display_name":"Mission College","ror":"https://ror.org/035fpgr29","country_code":"US","type":"education","lineage":["https://openalex.org/I4210128612"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. John Pennycook","raw_affiliation_strings":["Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210128612"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109346931","display_name":"Alejandro Dur\u00e1n","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210128612","display_name":"Mission College","ror":"https://ror.org/035fpgr29","country_code":"US","type":"education","lineage":["https://openalex.org/I4210128612"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alejandro Duran","raw_affiliation_strings":["Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210128612"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023057979","display_name":"Christian Terboven","orcid":"https://orcid.org/0000-0003-2284-2957"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Christian Terboven","raw_affiliation_strings":["High Performance Computing (I12), RWTH Aachen University, Seffenter Weg 23 52074 Aachen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"High Performance Computing (I12), RWTH Aachen University, Seffenter Weg 23 52074 Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020276955","display_name":"Xinmin Tian","orcid":"https://orcid.org/0000-0001-6228-924X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210128612","display_name":"Mission College","ror":"https://ror.org/035fpgr29","country_code":"US","type":"education","lineage":["https://openalex.org/I4210128612"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xinmin Tian","raw_affiliation_strings":["Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210128612"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087985063","display_name":"Ravi Narayanaswamy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210128612","display_name":"Mission College","ror":"https://ror.org/035fpgr29","country_code":"US","type":"education","lineage":["https://openalex.org/I4210128612"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ravi Narayanaswamy","raw_affiliation_strings":["Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, 3600 Mission College Boulevard, Santa Clara, California 95050, USA","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210128612"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.3592233,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"13","issue":"1","first_page":"70","last_page":"70"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8945223689079285},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.6084863543510437},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5922737717628479},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5832641124725342},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.560603141784668},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5550306439399719},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.526482343673706},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5264095664024353},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.519450843334198},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.47870802879333496},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4715312123298645},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4692642092704773},{"id":"https://openalex.org/keywords/bridge","display_name":"Bridge (graph theory)","score":0.4356904923915863},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.43170982599258423},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4274784028530121},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2818283438682556},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.2652423083782196}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8945223689079285},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.6084863543510437},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5922737717628479},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5832641124725342},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.560603141784668},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5550306439399719},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.526482343673706},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5264095664024353},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.519450843334198},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.47870802879333496},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4715312123298645},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4692642092704773},{"id":"https://openalex.org/C100776233","wikidata":"https://www.wikidata.org/wiki/Q2532492","display_name":"Bridge (graph theory)","level":2,"score":0.4356904923915863},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.43170982599258423},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4274784028530121},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2818283438682556},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.2652423083782196},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C126322002","wikidata":"https://www.wikidata.org/wiki/Q11180","display_name":"Internal medicine","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1504/ijhpcn.2019.097052","is_oa":true,"landing_page_url":"https://doi.org/10.1504/ijhpcn.2019.097052","pdf_url":"https://doi.org/10.1504/ijhpcn.2019.097052","source":{"id":"https://openalex.org/S159903936","display_name":"International Journal of High Performance Computing and Networking","issn_l":"1740-0562","issn":["1740-0562","1740-0570"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310317825","host_organization_name":"Inderscience Publishers","host_organization_lineage":["https://openalex.org/P4310317825"],"host_organization_lineage_names":["Inderscience Publishers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of High Performance Computing and Networking","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1504/ijhpcn.2019.097052","is_oa":true,"landing_page_url":"https://doi.org/10.1504/ijhpcn.2019.097052","pdf_url":"https://doi.org/10.1504/ijhpcn.2019.097052","source":{"id":"https://openalex.org/S159903936","display_name":"International Journal of High Performance Computing and Networking","issn_l":"1740-0562","issn":["1740-0562","1740-0570"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310317825","host_organization_name":"Inderscience Publishers","host_organization_lineage":["https://openalex.org/P4310317825"],"host_organization_lineage_names":["Inderscience Publishers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of High Performance Computing and Networking","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.5400000214576721,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2354036839","https://openalex.org/W4293054943","https://openalex.org/W4321458411","https://openalex.org/W4232365528","https://openalex.org/W2296275612","https://openalex.org/W4248614727","https://openalex.org/W2564569739","https://openalex.org/W1975444747","https://openalex.org/W1975901677","https://openalex.org/W1655459528"],"abstract_inverted_index":{"Modern":[0],"computers":[1],"with":[2,102],"multi-/many-core":[3],"processors":[4],"and":[5,10,23,34,59,64,90,98],"accelerators":[6],"feature":[7],"a":[8],"sophisticated":[9],"deep":[11],"memory":[12,22,85],"hierarchy,":[13],"potentially":[14],"including":[15],"distinct":[16],"main":[17],"memory,":[18,20],"high-bandwidth":[19],"texture":[21],"scratchpad":[24],"memory.":[25],"The":[26],"performance":[27],"characteristics":[28,83,92],"of":[29,40,50,84,93],"these":[30,62],"memories":[31],"are":[32],"varied,":[33],"studies":[35],"have":[36],"demonstrated":[37],"the":[38,51,70,82,91],"importance":[39],"using":[41],"them":[42],"effectively.":[43],"In":[44],"this":[45,75],"article,":[46],"we":[47],"explore":[48],"some":[49],"major":[52],"issues":[53],"in":[54],"developing":[55],"software":[56],"to":[57,69,73],"effectively":[58],"portably":[60],"implement":[61],"technologies":[63],"describe":[65],"enhancements":[66],"being":[67],"added":[68],"OpenMP":[71,104],"language":[72],"bridge":[74],"software-hardware":[76],"gap.":[77],"Our":[78],"proposal":[79],"separately":[80],"exposes":[81],"resources":[86],"(such":[87,95],"as":[88,96],"kind)":[89],"allocations":[94],"alignment),":[97],"is":[99],"fully":[100],"compatible":[101],"existing":[103],"constructs.":[105]},"counts_by_year":[{"year":2023,"cited_by_count":2}],"updated_date":"2026-08-04T08:18:43.703281","created_date":"2025-10-10T00:00:00"}