{"id":"https://openalex.org/W2596239367","doi":"https://doi.org/10.1504/ijcaet.2017.10003936","title":"Transistor level realisation of power gated FSM","display_name":"Transistor level realisation of power gated FSM","publication_year":2017,"publication_date":"2017-01-01","ids":{"openalex":"https://openalex.org/W2596239367","doi":"https://doi.org/10.1504/ijcaet.2017.10003936","mag":"2596239367"},"language":"en","primary_location":{"id":"doi:10.1504/ijcaet.2017.10003936","is_oa":false,"landing_page_url":"https://doi.org/10.1504/ijcaet.2017.10003936","pdf_url":null,"source":{"id":"https://openalex.org/S5114360","display_name":"International Journal of Computer Aided Engineering and Technology","issn_l":"1757-2657","issn":["1757-2657","1757-2665"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310317825","host_organization_name":"Inderscience Publishers","host_organization_lineage":["https://openalex.org/P4310317825"],"host_organization_lineage_names":["Inderscience Publishers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Computer Aided Engineering and Technology","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026845029","display_name":"Debanjali Nath","orcid":null},"institutions":[{"id":"https://openalex.org/I196486160","display_name":"National Institute of Technology Agartala","ror":"https://ror.org/03swyrn62","country_code":"IN","type":"education","lineage":["https://openalex.org/I196486160"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Debanjali Nath","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India","institution_ids":["https://openalex.org/I196486160"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002234378","display_name":"Priyanka Choudhury","orcid":"https://orcid.org/0000-0002-0917-0925"},"institutions":[{"id":"https://openalex.org/I196486160","display_name":"National Institute of Technology Agartala","ror":"https://ror.org/03swyrn62","country_code":"IN","type":"education","lineage":["https://openalex.org/I196486160"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Priyanka Choudhury","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India","institution_ids":["https://openalex.org/I196486160"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046717391","display_name":"Sambhu Nath Pradhan","orcid":"https://orcid.org/0000-0002-5461-6535"},"institutions":[{"id":"https://openalex.org/I196486160","display_name":"National Institute of Technology Agartala","ror":"https://ror.org/03swyrn62","country_code":"IN","type":"education","lineage":["https://openalex.org/I196486160"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sambhu Nath Pradhan","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Agartala, Tripura-799055, India","institution_ids":["https://openalex.org/I196486160"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5026845029"],"corresponding_institution_ids":["https://openalex.org/I196486160"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01828024,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":"3","first_page":"351","last_page":"351"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8202610015869141},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6988858580589294},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6546634435653687},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5884321331977844},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5173277854919434},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4973929226398468},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49404340982437134},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.47314369678497314},{"id":"https://openalex.org/keywords/realisation","display_name":"Realisation","score":0.47150105237960815},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.44811469316482544},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4210100769996643},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.41192036867141724},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3759225606918335},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3287857174873352},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2731584310531616},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.22504401206970215},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14866602420806885},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09517815709114075}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8202610015869141},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6988858580589294},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6546634435653687},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5884321331977844},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5173277854919434},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4973929226398468},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49404340982437134},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.47314369678497314},{"id":"https://openalex.org/C2779462738","wikidata":"https://www.wikidata.org/wiki/Q17146409","display_name":"Realisation","level":2,"score":0.47150105237960815},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.44811469316482544},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4210100769996643},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.41192036867141724},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3759225606918335},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3287857174873352},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2731584310531616},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.22504401206970215},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14866602420806885},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09517815709114075},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1504/ijcaet.2017.10003936","is_oa":false,"landing_page_url":"https://doi.org/10.1504/ijcaet.2017.10003936","pdf_url":null,"source":{"id":"https://openalex.org/S5114360","display_name":"International Journal of Computer Aided Engineering and Technology","issn_l":"1757-2657","issn":["1757-2657","1757-2665"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310317825","host_organization_name":"Inderscience Publishers","host_organization_lineage":["https://openalex.org/P4310317825"],"host_organization_lineage_names":["Inderscience Publishers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Computer Aided Engineering and Technology","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2535130387","https://openalex.org/W4248668797","https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W3141297747","https://openalex.org/W2106889348","https://openalex.org/W2111485030","https://openalex.org/W4390345338","https://openalex.org/W96064250","https://openalex.org/W2141941412"],"abstract_inverted_index":{"Power":[0,18,134],"can":[1],"be":[2,33],"minimised":[3],"for":[4,35],"the":[5,47],"power":[6,39,52,65,80,128,132,147],"gated":[7,40,129],"finite":[8],"state":[9],"machine":[10],"(FSM)":[11],"by":[12,130],"suitable":[13],"partitioning":[14],"and":[15,29,78,97,145],"encoding":[16,98],"strategy.":[17],"gating":[19,66,135],"architecture":[20,63,113],"designed":[21,115],"previously":[22],"at":[23,118],"FSM":[24,100],"level":[25,74],"is":[26,114,127],"hypothetical":[27],"one":[28,125],"may":[30],"not":[31],"directly":[32],"used":[34],"practical":[36],"implementation":[37],"of":[38,46,54,64,82,99,105,143,149],"circuit":[41,71,108],"in":[42,72,137],"transistor":[43,73],"level.":[44],"Most":[45],"previous":[48],"works":[49],"concern":[50],"about":[51],"reduction":[53],"combinational":[55,83,121],"parts":[56],"only.":[57],"In":[58],"this":[59,138],"work,":[60],"a":[61,119],"new":[62],"design":[67],"which":[68],"implements":[69],"sequential":[70,87,90],"has":[75,109],"been":[76,110],"proposed":[77],"considers":[79],"consumption":[81],"as":[84,86],"well":[85],"parts.":[88],"The":[89,112],"circuits":[91,122],"are":[92],"obtained":[93],"after":[94],"concurrent":[95],"bi-partitioning":[96],"benchmark":[101],"circuit.":[102],"Multi-level":[103],"realisation":[104],"two-level":[106],"PLA":[107],"done.":[111],"such":[116],"that":[117],"time":[120],"corresponding":[123],"to":[124],"sub-FSM":[126],"shutting-OFF":[131],"supply.":[133],"technique":[136],"work":[139],"shows":[140],"leakage":[141],"saving":[142,148],"47%":[144],"total":[146],"53.6%.":[150]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
