{"id":"https://openalex.org/W2166955231","doi":"https://doi.org/10.14778/1454159.1454171","title":"Efficient implementation of sorting on multi-core SIMD CPU architecture","display_name":"Efficient implementation of sorting on multi-core SIMD CPU architecture","publication_year":2008,"publication_date":"2008-08-01","ids":{"openalex":"https://openalex.org/W2166955231","doi":"https://doi.org/10.14778/1454159.1454171","mag":"2166955231"},"language":"en","primary_location":{"id":"doi:10.14778/1454159.1454171","is_oa":false,"landing_page_url":"https://doi.org/10.14778/1454159.1454171","pdf_url":null,"source":{"id":"https://openalex.org/S4210226185","display_name":"Proceedings of the VLDB Endowment","issn_l":"2150-8097","issn":["2150-8097"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the VLDB Endowment","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059686266","display_name":"Jatin Chhugani","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jatin Chhugani","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047809126","display_name":"Anthony D. Nguyen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Anthony D. Nguyen","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109971580","display_name":"Victor W. Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Victor W. Lee","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050525624","display_name":"W. Macy","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"William Macy","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066708965","display_name":"Mostafa Hagog","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Mostafa Hagog","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042651234","display_name":"Yen-Kuang Chen","orcid":"https://orcid.org/0000-0003-4546-9497"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Yen-Kuang Chen","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045809293","display_name":"Akram Baransi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Akram Baransi","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102012468","display_name":"Sanjeev Kumar","orcid":"https://orcid.org/0000-0001-9065-3010"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Sanjeev Kumar","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032238070","display_name":"Pradeep Dubey","orcid":"https://orcid.org/0000-0001-5853-0619"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Pradeep Dubey","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":17.2662,"has_fulltext":false,"cited_by_count":228,"citation_normalized_percentile":{"value":0.9937297,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":100},"biblio":{"volume":"1","issue":"2","first_page":"1313","last_page":"1324"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.8914248943328857},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8624044060707092},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.8124198317527771},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7253057956695557},{"id":"https://openalex.org/keywords/merge-sort","display_name":"Merge sort","score":0.5666546821594238},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.5094466805458069},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4588854908943176},{"id":"https://openalex.org/keywords/sorting-algorithm","display_name":"Sorting algorithm","score":0.4397856593132019},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.43471086025238037},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3568449318408966},{"id":"https://openalex.org/keywords/sorting","display_name":"Sorting","score":0.34105783700942993},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17087996006011963},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12181165814399719},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.10071679949760437}],"concepts":[{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.8914248943328857},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8624044060707092},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.8124198317527771},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7253057956695557},{"id":"https://openalex.org/C35555965","wikidata":"https://www.wikidata.org/wiki/Q189057","display_name":"Merge sort","level":4,"score":0.5666546821594238},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.5094466805458069},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4588854908943176},{"id":"https://openalex.org/C108094655","wikidata":"https://www.wikidata.org/wiki/Q181593","display_name":"Sorting algorithm","level":3,"score":0.4397856593132019},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43471086025238037},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3568449318408966},{"id":"https://openalex.org/C111696304","wikidata":"https://www.wikidata.org/wiki/Q2303697","display_name":"Sorting","level":2,"score":0.34105783700942993},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17087996006011963},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12181165814399719},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.10071679949760437}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.14778/1454159.1454171","is_oa":false,"landing_page_url":"https://doi.org/10.14778/1454159.1454171","pdf_url":null,"source":{"id":"https://openalex.org/S4210226185","display_name":"Proceedings of the VLDB Endowment","issn_l":"2150-8097","issn":["2150-8097"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the VLDB Endowment","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.140.8757","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.140.8757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"http://www.vldb.org/pvldb/1/1454171.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W100509257","https://openalex.org/W1528478977","https://openalex.org/W1985559048","https://openalex.org/W1995596660","https://openalex.org/W2007519459","https://openalex.org/W2037743346","https://openalex.org/W2051374083","https://openalex.org/W2111435979","https://openalex.org/W2118558147","https://openalex.org/W2119547137","https://openalex.org/W2125357468","https://openalex.org/W2127766448","https://openalex.org/W2141389982","https://openalex.org/W2151771061","https://openalex.org/W2153952995","https://openalex.org/W2155119349","https://openalex.org/W2160204225","https://openalex.org/W2169150396","https://openalex.org/W2240847203","https://openalex.org/W2752061190","https://openalex.org/W2752853835","https://openalex.org/W4211164170","https://openalex.org/W4247913514","https://openalex.org/W6678107477","https://openalex.org/W6690161281"],"related_works":["https://openalex.org/W2129537883","https://openalex.org/W2911551207","https://openalex.org/W4225987401","https://openalex.org/W4226140811","https://openalex.org/W2765396134","https://openalex.org/W4236526691","https://openalex.org/W2003690377","https://openalex.org/W4312862090","https://openalex.org/W1480783219","https://openalex.org/W2153952995"],"abstract_inverted_index":{"Sorting":[0],"a":[1,108],"list":[2],"of":[3,8,16,33,56,129,141,157,165,180,192,201],"input":[4],"numbers":[5,101],"is":[6,68,85],"one":[7],"the":[9,14,72,89,124,130],"most":[10],"fundamental":[11],"problems":[12],"in":[13,19,25,102],"field":[15],"computer":[17],"science":[18],"general":[20],"and":[21,53,84,150,182],"high-throughput":[22],"database":[23],"applications":[24],"particular.":[26],"Although":[27],"literature":[28],"abounds":[29],"with":[30,65,118,134,168],"various":[31,158],"flavors":[32],"sorting":[34,45,132],"algorithms,":[35],"different":[36],"architectures":[37],"call":[38],"for":[39],"customized":[40],"implementations":[41],"to":[42,136,173],"achieve":[43],"faster":[44,70],"times.":[46],"This":[47,113],"paper":[48,125],"presents":[49],"an":[50,80],"efficient":[51,81],"implementation":[52,64,95,167],"detailed":[54],"analysis":[55],"MergeSort":[57],"on":[58,107,153],"current":[59,177],"CPU":[60],"architectures.":[61],"Our":[62,92],"SIMD":[63,94,148,169],"128-bit":[66],"SSE":[67,178],"3.3X":[69],"than":[71,104,176],"scalar":[73],"version.":[74],"In":[75],"addition,":[76],"our":[77,154,166,202],"algorithm":[78,133],"performs":[79],"multiway":[82],"merge,":[83],"not":[86],"constrained":[87],"by":[88],"memory":[90],"bandwidth.":[91],"multi-threaded,":[93],"sorts":[96],"64":[97],"million":[98],"floating":[99],"point":[100],"less":[103],"0.5":[105],"seconds":[106],"commodity":[109],"4-core":[110],"Intel":[111],"processor.":[112],"measured":[114],"performance":[115,127],"compares":[116],"favorably":[117],"all":[119],"previously":[120],"published":[121],"results.":[122],"Additionally,":[123],"demonstrates":[126],"scalability":[128,164,200],"proposed":[131,203],"respect":[135],"certain":[137],"salient":[138],"architectural":[139,159],"features":[140],"modern":[142],"chip":[143],"multiprocessor":[144],"(CMP)":[145],"architectures,":[146],"including":[147],"width":[149,170,179],"core-count.":[151],"Based":[152],"analytical":[155],"models":[156],"configurations,":[160],"we":[161],"see":[162],"excellent":[163],"scaling":[171,185],"up":[172],"16X":[174],"wider":[175],"128-bits,":[181],"CMP":[183],"core-count":[184],"well":[186],"beyond":[187],"32":[188],"cores.":[189],"Cycle-accurate":[190],"simulation":[191],"Intel's":[193],"upcoming":[194],"x86":[195],"many-core":[196],"Larrabee":[197],"architecture":[198],"confirms":[199],"algorithm.":[204]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":9},{"year":2021,"cited_by_count":20},{"year":2020,"cited_by_count":12},{"year":2019,"cited_by_count":15},{"year":2018,"cited_by_count":11},{"year":2017,"cited_by_count":14},{"year":2016,"cited_by_count":16},{"year":2015,"cited_by_count":20},{"year":2014,"cited_by_count":17},{"year":2013,"cited_by_count":8},{"year":2012,"cited_by_count":18}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}