{"id":"https://openalex.org/W2985423753","doi":"https://doi.org/10.1155/2019/2624938","title":"Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise\u2014Designing a Computer Architecture via HLS)","display_name":"Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise\u2014Designing a Computer Architecture via HLS)","publication_year":2019,"publication_date":"2019-11-03","ids":{"openalex":"https://openalex.org/W2985423753","doi":"https://doi.org/10.1155/2019/2624938","mag":"2985423753"},"language":"en","primary_location":{"id":"doi:10.1155/2019/2624938","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2019/2624938","pdf_url":"https://downloads.hindawi.com/journals/ijrc/2019/2624938.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://downloads.hindawi.com/journals/ijrc/2019/2624938.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012892451","display_name":"Roberto Giorgi","orcid":"https://orcid.org/0000-0003-0384-8229"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Roberto Giorgi","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"raw_orcid":"https://orcid.org/0000-0003-0384-8229","affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051663655","display_name":"Farnam Khalili","orcid":"https://orcid.org/0000-0003-2307-139X"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]},{"id":"https://openalex.org/I45084792","display_name":"University of Florence","ror":"https://ror.org/04jr1s763","country_code":"IT","type":"education","lineage":["https://openalex.org/I45084792"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Farnam Khalili","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","Department of Information Engineering, University of Florence, Florence, Italy"],"raw_orcid":"https://orcid.org/0000-0003-2307-139X","affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]},{"raw_affiliation_string":"Department of Information Engineering, University of Florence, Florence, Italy","institution_ids":["https://openalex.org/I45084792"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040116044","display_name":"Marco Procaccini","orcid":"https://orcid.org/0000-0002-9719-2672"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Procaccini","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"raw_orcid":"https://orcid.org/0000-0002-9719-2672","affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5012892451"],"corresponding_institution_ids":["https://openalex.org/I102064193"],"apc_list":{"value":925,"currency":"USD","value_usd":925},"apc_paid":{"value":925,"currency":"USD","value_usd":925},"fwci":1.0384,"has_fulltext":true,"cited_by_count":6,"citation_normalized_percentile":{"value":0.78366225,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"2019","issue":null,"first_page":"1","last_page":"18"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8521043062210083},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6912464499473572},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5687515139579773},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5512033700942993},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5385532975196838},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5312932133674622},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5136451125144958},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.501356840133667},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.4984312057495117},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.43562036752700806},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4322672486305237},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15998488664627075}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8521043062210083},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6912464499473572},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5687515139579773},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5512033700942993},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5385532975196838},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5312932133674622},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5136451125144958},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.501356840133667},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.4984312057495117},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.43562036752700806},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4322672486305237},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15998488664627075},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1155/2019/2624938","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2019/2624938","pdf_url":"https://downloads.hindawi.com/journals/ijrc/2019/2624938.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},{"id":"pmh:oai:usiena-air.unisi.it:11365/1081837","is_oa":true,"landing_page_url":"http://hdl.handle.net/11365/1081837","pdf_url":"http://hdl.handle.net/11365/1081837","source":{"id":"https://openalex.org/S4377196319","display_name":"Use Siena air (University of Siena)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I102064193","host_organization_name":"University of Siena","host_organization_lineage":["https://openalex.org/I102064193"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:doaj.org/article:e502f6d991884c7196e0a25b515f62e8","is_oa":false,"landing_page_url":"https://doaj.org/article/e502f6d991884c7196e0a25b515f62e8","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"International Journal of Reconfigurable Computing, Vol 2019 (2019)","raw_type":"article"},{"id":"pmh:oai:zenodo.org:105933","is_oa":true,"landing_page_url":"https://www.openaccessrepository.it/record/105933","pdf_url":null,"source":{"id":"https://openalex.org/S4306402478","display_name":"INFM-OAR (INFN Catania)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210116497","host_organization_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Catania","host_organization_lineage":["https://openalex.org/I4210116497"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"doi:10.1155/2019/2624938","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2019/2624938","pdf_url":"https://downloads.hindawi.com/journals/ijrc/2019/2624938.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.6399999856948853,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G3210734087","display_name":"Agile, eXtensible, fast I/O Module for the cyber-physical era","funder_award_id":"645496","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G4937468798","display_name":null,"funder_award_id":"H2020","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G5685409767","display_name":"Exploiting dataflow parallelism in Teradevice Computing","funder_award_id":"249013","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G7004203353","display_name":null,"funder_award_id":"779656","funder_id":"https://openalex.org/F4320332999","funder_display_name":"Horizon 2020 Framework Programme"},{"id":"https://openalex.org/G876947219","display_name":"High Performance and Embedded Architecture and Compilation","funder_award_id":"779656","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320332999","display_name":"Horizon 2020 Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2985423753.pdf","grobid_xml":"https://content.openalex.org/works/W2985423753.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W1864199185","https://openalex.org/W1983899098","https://openalex.org/W2001408484","https://openalex.org/W2018936045","https://openalex.org/W2073983509","https://openalex.org/W2092185683","https://openalex.org/W2104225326","https://openalex.org/W2134633067","https://openalex.org/W2140130374","https://openalex.org/W2164264749","https://openalex.org/W2621380892","https://openalex.org/W2888147629"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2274562545","https://openalex.org/W2612099726","https://openalex.org/W3146054601","https://openalex.org/W2269990635","https://openalex.org/W2029518208","https://openalex.org/W4285464654","https://openalex.org/W3013057549","https://openalex.org/W2906427691","https://openalex.org/W2507786429"],"abstract_inverted_index":{"Translating":[0],"a":[1,5,57,71,107,111,128,155,200,209],"system":[2,109,189],"requirement":[3],"into":[4,176],"low-level":[6],"representation":[7],"(e.g.,":[8],"register":[9],"transfer":[10],"level":[11,73],"or":[12],"RTL)":[13],"is":[14,65],"the":[15,19,25,33,63,81,145,151,164,174,177,182,191,206,223,234,241],"typical":[16],"goal":[17],"of":[18,21,106,158,186,208,225],"design":[20,105,117,152,175],"FPGA-based":[22],"systems.":[23],"However,":[24],"Design":[26],"Space":[27],"Exploration":[28],"(DSE)":[29],"needed":[30],"to":[31,80,101,116,126,231,246],"identify":[32],"final":[34],"architecture":[35],"may":[36],"be":[37],"time":[38,113,243],"consuming,":[39],"even":[40],"when":[41],"using":[42,70,144],"high-level":[43],"synthesis":[44],"(HLS)":[45],"tools.":[46],"In":[47,94],"this":[48,96,195,219],"article,":[49],"we":[50,197,214,217,228],"illustrate":[51],"our":[52,89,159,168,187],"hybrid":[53],"methodology,":[54],"which":[55,237],"uses":[56],"frontend":[58],"for":[59],"HLS":[60,146,179],"so":[61],"that":[62,141,227],"DSE":[64,90],"performed":[66],"more":[67],"rapidly":[68],"by":[69],"higher":[72],"abstraction,":[74],"but":[75],"without":[76],"losing":[77],"accuracy,":[78],"thanks":[79],"HP-Labs":[82],"COTSon":[83],"simulation":[84,169],"infrastructure":[85],"in":[86,110,120,150,162,167,190,205,233],"combination":[87],"with":[88],"tools":[91],"(MYDSE":[92],"tools).":[93],"particular,":[95],"proposed":[97],"methodology":[98,160,220],"proved":[99],"useful":[100],"achieve":[102],"an":[103],"appropriate":[104],"whole":[108],"shorter":[112],"than":[114],"trying":[115],"everything":[118],"directly":[119,143],"HLS.":[121],"Our":[122],"motivating":[123],"problem":[124],"was":[125,147],"deploy":[127],"novel":[129,188],"execution":[130],"model":[131],"called":[132],"data-flow":[133],"threads":[134],"(DF-Threads)":[135],"running":[136],"on":[137],"yet-to-be-designed":[138],"hardware.":[139],"For":[140],"goal,":[142],"too":[148],"premature":[149],"cycle.":[153],"Therefore,":[154],"key":[156,183],"point":[157],"consists":[161],"defining":[163],"first":[165,198],"prototype":[166],"framework":[170],"and":[171,221],"gradually":[172],"migrating":[173],"Xilinx":[178],"after":[180],"validating":[181],"performance":[184],"metrics":[185],"simulator.":[192],"To":[193],"explain":[194,215],"workflow,":[196],"use":[199],"simple":[201],"driving":[202],"example":[203],"consisting":[204],"modelling":[207],"two-way":[210],"associative":[211],"cache.":[212],"Then,":[213],"how":[216],"generalized":[218],"describe":[222],"types":[224],"results":[226],"were":[229],"able":[230],"analyze":[232],"AXIOM":[235],"project,":[236],"helped":[238],"us":[239],"reduce":[240],"development":[242],"from":[244],"months/weeks":[245],"days/hours.":[247]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2}],"updated_date":"2026-08-15T07:11:24.734988","created_date":"2019-11-22T00:00:00"}