{"id":"https://openalex.org/W2540619780","doi":"https://doi.org/10.1155/2016/8093614","title":"A Cache System Design for CMPs with Built-In Coherence Verification","display_name":"A Cache System Design for CMPs with Built-In Coherence Verification","publication_year":2016,"publication_date":"2016-10-30","ids":{"openalex":"https://openalex.org/W2540619780","doi":"https://doi.org/10.1155/2016/8093614","mag":"2540619780"},"language":"en","primary_location":{"id":"doi:10.1155/2016/8093614","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2016/8093614","pdf_url":"https://downloads.hindawi.com/archive/2016/8093614.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2016/8093614.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024913744","display_name":"Mamata Dalui","orcid":"https://orcid.org/0000-0001-5829-541X"},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Mamata Dalui","raw_affiliation_strings":["Department of Computer Science and Engineering, National Institute of Technology Durgapur, West Bengal 713209, India"],"raw_orcid":"https://orcid.org/0000-0001-5829-541X","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Institute of Technology Durgapur, West Bengal 713209, India","institution_ids":["https://openalex.org/I155837530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089134920","display_name":"Biplab K. Sikdar","orcid":"https://orcid.org/0000-0002-9394-8540"},"institutions":[{"id":"https://openalex.org/I98365261","display_name":"Indian Institute of Engineering Science and Technology, Shibpur","ror":"https://ror.org/02ytfzr55","country_code":"IN","type":"education","lineage":["https://openalex.org/I98365261"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Biplab K. Sikdar","raw_affiliation_strings":["Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology Shibpur, West Bengal 711103, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology Shibpur, West Bengal 711103, India","institution_ids":["https://openalex.org/I98365261"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5024913744"],"corresponding_institution_ids":["https://openalex.org/I155837530"],"apc_list":null,"apc_paid":null,"fwci":0.7209,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.76501865,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"2016","issue":null,"first_page":"1","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.8570755124092102},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8266575336456299},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7386270761489868},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.7208858728408813},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.5914621353149414},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5676620602607727},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5673170685768127},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5531066656112671},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.5185878276824951},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.49980831146240234},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4736831486225128},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.4371255338191986},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41832536458969116}],"concepts":[{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.8570755124092102},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8266575336456299},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7386270761489868},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.7208858728408813},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.5914621353149414},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5676620602607727},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5673170685768127},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5531066656112671},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.5185878276824951},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.49980831146240234},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4736831486225128},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.4371255338191986},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41832536458969116}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2016/8093614","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2016/8093614","pdf_url":"https://downloads.hindawi.com/archive/2016/8093614.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2016/8093614","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2016/8093614","pdf_url":"https://downloads.hindawi.com/archive/2016/8093614.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2540619780.pdf","grobid_xml":"https://content.openalex.org/works/W2540619780.grobid-xml"},"referenced_works_count":24,"referenced_works":["https://openalex.org/W124329337","https://openalex.org/W1555915743","https://openalex.org/W1581074884","https://openalex.org/W1967643097","https://openalex.org/W1981369369","https://openalex.org/W2003566819","https://openalex.org/W2007053448","https://openalex.org/W2033263591","https://openalex.org/W2038509324","https://openalex.org/W2043569543","https://openalex.org/W2103742924","https://openalex.org/W2123859627","https://openalex.org/W2126603706","https://openalex.org/W2136263143","https://openalex.org/W2136895826","https://openalex.org/W2145021036","https://openalex.org/W2146784273","https://openalex.org/W2152450729","https://openalex.org/W2153184575","https://openalex.org/W2153904572","https://openalex.org/W2166615043","https://openalex.org/W2169387321","https://openalex.org/W2240192597","https://openalex.org/W2539882325"],"related_works":["https://openalex.org/W4312759433","https://openalex.org/W4304166325","https://openalex.org/W2290179447","https://openalex.org/W273173017","https://openalex.org/W2046654858","https://openalex.org/W2184371594","https://openalex.org/W2148571123","https://openalex.org/W1521238853","https://openalex.org/W2801630946","https://openalex.org/W2152423944"],"abstract_inverted_index":{"This":[0],"work":[1],"reports":[2],"an":[3,123],"effective":[4],"design":[5],"of":[6,19,48,71,81,91,133,139,141,158,179,189],"cache":[7,20,68,84,93,115,134,205],"system":[8,85],"for":[9,17,168],"Chip":[10],"Multiprocessors":[11],"(CMPs).":[12],"It":[13,28],"introduces":[14],"built-in":[15],"logic":[16,171],"verification":[18,163,170,182,192],"coherence":[21,79,181],"in":[22,42,67,150,161,203],"CMPs":[23],"realizing":[24],"directory":[25],"based":[26],"protocol.":[27],"is":[29,184,195],"developed":[30,107],"around":[31],"the":[32,43,65,82,92,97,114,142,152,156,162,169,174,177,190,200],"cellular":[33,57],"automata":[34,58],"(CA)":[35],"machine,":[36],"invented":[37],"by":[38,154],"John":[39],"von":[40],"Neumann":[41],"1950s.":[44],"A":[45],"special":[46],"class":[47],"CA":[49],"referred":[50],"to":[51,63,100,108,112,120,122,173,199],"as":[52],"single":[53],"length":[54],"cycle":[55],"2-attractor":[56],"(TACA)":[59],"has":[60,105],"been":[61,106],"planted":[62],"detect":[64],"inconsistencies":[66],"line":[69,94,135],"states":[70,95],"processors\u2019":[72,98],"private":[73],"caches.":[74],"The":[75,137,165],"TACA":[76,111],"module":[77,183],"captures":[78],"status":[80],"CMPs\u2019":[83,143,204],"and":[86,118,194],"memorizes":[87],"any":[88],"inconsistent":[89],"recording":[90,132],"during":[96],"reference":[99],"a":[101,110,130,147],"memory":[102],"block.":[103],"Theory":[104],"empower":[109],"analyse":[113],"state":[116,125],"updates":[117],"then":[119],"settle":[121],"attractor":[124],"indicating":[126],"quick":[127],"decision":[128],"on":[129],"faulty":[131],"status.":[136],"introduction":[138],"segmentation":[140],"processor":[144],"pool":[145],"ensures":[146],"better":[148],"efficiency,":[149],"determining":[151],"inconsistencies,":[153],"reducing":[155],"number":[157],"computation":[159],"steps":[160],"logic.":[164],"hardware":[166],"requirement":[167],"points":[172],"fact":[175],"that":[176,188],"overhead":[178],"proposed":[180],"much":[185],"lesser":[186],"than":[187],"conventional":[191],"units":[193],"insignificant":[196],"with":[197],"respect":[198],"cost":[201],"involved":[202],"system.":[206]},"counts_by_year":[{"year":2018,"cited_by_count":2}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
