{"id":"https://openalex.org/W2262632074","doi":"https://doi.org/10.1155/2015/826283","title":"A Scalable Unsegmented Multiport Memory for FPGA-Based Systems","display_name":"A Scalable Unsegmented Multiport Memory for FPGA-Based Systems","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W2262632074","doi":"https://doi.org/10.1155/2015/826283","mag":"2262632074"},"language":"en","primary_location":{"id":"doi:10.1155/2015/826283","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2015/826283","pdf_url":"http://downloads.hindawi.com/journals/ijrc/2015/826283.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"http://downloads.hindawi.com/journals/ijrc/2015/826283.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032062942","display_name":"Kevin R. Townsend","orcid":null},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin R. Townsend","raw_affiliation_strings":["Reconfigurable Computing Laboratory, Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Laboratory, Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078669544","display_name":"Osama G. Attia","orcid":"https://orcid.org/0000-0002-7663-5534"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Osama G. Attia","raw_affiliation_strings":["Reconfigurable Computing Laboratory, Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Laboratory, Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026774201","display_name":"Phillip H. Jones","orcid":"https://orcid.org/0000-0002-8220-7552"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Phillip H. Jones","raw_affiliation_strings":["Reconfigurable Computing Laboratory, Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Laboratory, Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA","institution_ids":["https://openalex.org/I173911158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081541206","display_name":"Joseph Zambreno","orcid":"https://orcid.org/0000-0002-0566-5744"},"institutions":[{"id":"https://openalex.org/I173911158","display_name":"Iowa State University","ror":"https://ror.org/04rswrd78","country_code":"US","type":"education","lineage":["https://openalex.org/I173911158"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Joseph Zambreno","raw_affiliation_strings":["Reconfigurable Computing Laboratory, Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA"],"raw_orcid":"https://orcid.org/0000-0002-0566-5744","affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Laboratory, Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA","institution_ids":["https://openalex.org/I173911158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5081541206"],"corresponding_institution_ids":["https://openalex.org/I173911158"],"apc_list":{"value":900,"currency":"USD","value_usd":900},"apc_paid":{"value":900,"currency":"USD","value_usd":900},"fwci":0.3294,"has_fulltext":true,"cited_by_count":9,"citation_normalized_percentile":{"value":0.62817412,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"2015","issue":null,"first_page":"1","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8302776217460632},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6767719984054565},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5844379663467407},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.565101146697998},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5471190810203552},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5223665833473206},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5104423761367798},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5088901519775391},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.50026535987854},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.4590088725090027},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.43978822231292725},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.42134860157966614},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.40673285722732544},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30451592803001404},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11931028962135315}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8302776217460632},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6767719984054565},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5844379663467407},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.565101146697998},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5471190810203552},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5223665833473206},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5104423761367798},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5088901519775391},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.50026535987854},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.4590088725090027},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.43978822231292725},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.42134860157966614},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.40673285722732544},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30451592803001404},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11931028962135315}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1155/2015/826283","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2015/826283","pdf_url":"http://downloads.hindawi.com/journals/ijrc/2015/826283.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},{"id":"pmh:oai:lib.dr.iastate.edu:ece_pubs-1102","is_oa":true,"landing_page_url":"https://lib.dr.iastate.edu/ece_pubs/102","pdf_url":null,"source":{"id":"https://openalex.org/S4377196104","display_name":"Iowa State University Digital Repository (Iowa State University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I173911158","host_organization_name":"Iowa State University","host_organization_lineage":["https://openalex.org/I173911158"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical and Computer Engineering Publications","raw_type":"text"},{"id":"pmh:oai:doaj.org/article:5649e924e5c94edd83c371c490e2b504","is_oa":true,"landing_page_url":"https://doaj.org/article/5649e924e5c94edd83c371c490e2b504","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"International Journal of Reconfigurable Computing, Vol 2015 (2015)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2015/826283","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2015/826283","pdf_url":"http://downloads.hindawi.com/journals/ijrc/2015/826283.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/8"}],"awards":[{"id":"https://openalex.org/G2063233596","display_name":"CSR: Small:  Hardware Architectures for Data Mining at the Exascale","funder_award_id":"1116810","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G3153839890","display_name":"CAREER:  Architectural Support for CPU / GPU Hybridization","funder_award_id":"1149539","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6473885579","display_name":null,"funder_award_id":"CNS-1116810","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6973344255","display_name":null,"funder_award_id":"CCF-1149539","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2262632074.pdf","grobid_xml":"https://content.openalex.org/works/W2262632074.grobid-xml"},"referenced_works_count":18,"referenced_works":["https://openalex.org/W1482836228","https://openalex.org/W1972821547","https://openalex.org/W1995348478","https://openalex.org/W2009398166","https://openalex.org/W2014882201","https://openalex.org/W2017503457","https://openalex.org/W2024080903","https://openalex.org/W2027069801","https://openalex.org/W2044548351","https://openalex.org/W2054926865","https://openalex.org/W2093994565","https://openalex.org/W2094224213","https://openalex.org/W2121076909","https://openalex.org/W2123051253","https://openalex.org/W2129565950","https://openalex.org/W2132996124","https://openalex.org/W2164309468","https://openalex.org/W2164361660"],"related_works":["https://openalex.org/W2155373950","https://openalex.org/W2753615087","https://openalex.org/W3048967625","https://openalex.org/W2138825797","https://openalex.org/W4379620206","https://openalex.org/W4243618206","https://openalex.org/W2587873888","https://openalex.org/W4248614727","https://openalex.org/W2296275612","https://openalex.org/W4293054943"],"abstract_inverted_index":{"On-chip":[0],"multiport":[1,51,98],"memory":[2,20,52,63,90,99,103,121],"cores":[3,21,53,100],"are":[4,55],"crucial":[5],"primitives":[6],"for":[7,18,49,57],"many":[8],"modern":[9],"high-performance":[10],"reconfigurable":[11,58],"architectures":[12],"and":[13,31,77,94],"multicore":[14],"systems.":[15],"Previous":[16],"approaches":[17,48,69],"scaling":[19,83],"come":[22],"at":[23],"the":[24,36,40,141],"cost":[25],"of":[26,39,143],"operating":[27],"frequency,":[28],"communication":[29],"overhead,":[30],"logic":[32,86],"resources":[33],"without":[34,84],"increasing":[35],"storage":[37],"capacity":[38],"memory.":[41],"In":[42],"this":[43],"paper,":[44],"we":[45,95],"present":[46],"two":[47],"designing":[50],"that":[54,138],"suitable":[56],"accelerators":[59],"with":[60,117,135,140],"substantial":[61],"on-chip":[62],"or":[64],"complex":[65],"communication.":[66],"Our":[67,128],"design":[68,111],"tackle":[70],"these":[71],"challenges":[72],"by":[73],"banking":[74],"RAM":[75],"blocks":[76],"utilizing":[78],"interconnect":[79],"networks":[80],"which":[81],"allows":[82],"sacrificing":[85],"resources.":[87],"With":[88],"banking,":[89],"congestion":[91],"is":[92],"unavoidable":[93],"evaluate":[96],"our":[97,115],"under":[101],"different":[102,110],"access":[104],"patterns":[105],"to":[106,119],"gain":[107],"insights":[108],"about":[109],"trade-offs.":[112],"We":[113],"demonstrate":[114],"implementation":[116],"up":[118],"256":[120],"ports":[122],"using":[123],"a":[124],"Xilinx":[125],"Virtex-7":[126],"FPGA.":[127],"experimental":[129],"results":[130],"report":[131],"high":[132],"throughput":[133],"memories":[134],"resource":[136],"usage":[137],"scales":[139],"number":[142],"ports.":[144]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}