{"id":"https://openalex.org/W1999071870","doi":"https://doi.org/10.1155/2015/651785","title":"A Discrete Event System Approach to Online Testing of Speed Independent Circuits","display_name":"A Discrete Event System Approach to Online Testing of Speed Independent Circuits","publication_year":2015,"publication_date":"2015-04-30","ids":{"openalex":"https://openalex.org/W1999071870","doi":"https://doi.org/10.1155/2015/651785","mag":"1999071870"},"language":"en","primary_location":{"id":"doi:10.1155/2015/651785","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2015/651785","pdf_url":"https://downloads.hindawi.com/archive/2015/651785.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2015/651785.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055447641","display_name":"Pradeep Kumar Biswal","orcid":"https://orcid.org/0000-0001-5687-8179"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P. K. Biswal","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039719257","display_name":"Kush Mishra","orcid":null},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. Mishra","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052215348","display_name":"Santosh Biswas","orcid":"https://orcid.org/0000-0003-3020-4154"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"S. Biswas","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070605948","display_name":"Hemangee K. Kapoor","orcid":"https://orcid.org/0000-0002-9376-7686"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"H. K. Kapoor","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati 781 039, India","institution_ids":["https://openalex.org/I1317621060"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5052215348"],"corresponding_institution_ids":["https://openalex.org/I1317621060"],"apc_list":null,"apc_paid":null,"fwci":0.323,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.58673515,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"2015","issue":null,"first_page":"1","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/semaphore","display_name":"Semaphore","score":0.8356509208679199},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.8145837783813477},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7448147535324097},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.728225588798523},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6667051315307617},{"id":"https://openalex.org/keywords/event","display_name":"Event (particle physics)","score":0.584685742855072},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5107378959655762},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5099822282791138},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4853600561618805},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.47791653871536255},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.460768461227417},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.46028226613998413},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4514238238334656},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4376991093158722},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.42881307005882263},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3728976249694824},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3450380265712738},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33925575017929077},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.16633352637290955},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1653384268283844},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13218006491661072},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08755385875701904},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08651459217071533}],"concepts":[{"id":"https://openalex.org/C95203288","wikidata":"https://www.wikidata.org/wiki/Q221682","display_name":"Semaphore","level":2,"score":0.8356509208679199},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.8145837783813477},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7448147535324097},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.728225588798523},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6667051315307617},{"id":"https://openalex.org/C2779662365","wikidata":"https://www.wikidata.org/wiki/Q5416694","display_name":"Event (particle physics)","level":2,"score":0.584685742855072},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5107378959655762},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5099822282791138},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4853600561618805},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.47791653871536255},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.460768461227417},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.46028226613998413},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4514238238334656},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4376991093158722},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.42881307005882263},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3728976249694824},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3450380265712738},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33925575017929077},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.16633352637290955},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1653384268283844},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13218006491661072},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08755385875701904},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08651459217071533},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2015/651785","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2015/651785","pdf_url":"https://downloads.hindawi.com/archive/2015/651785.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2015/651785","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2015/651785","pdf_url":"https://downloads.hindawi.com/archive/2015/651785.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1999071870.pdf","grobid_xml":"https://content.openalex.org/works/W1999071870.grobid-xml"},"referenced_works_count":30,"referenced_works":["https://openalex.org/W1547948144","https://openalex.org/W1577323490","https://openalex.org/W1603505953","https://openalex.org/W1906369229","https://openalex.org/W1927459197","https://openalex.org/W1982882557","https://openalex.org/W1985787415","https://openalex.org/W1996638359","https://openalex.org/W2028137247","https://openalex.org/W2035720669","https://openalex.org/W2064418024","https://openalex.org/W2088302981","https://openalex.org/W2106714226","https://openalex.org/W2116587035","https://openalex.org/W2121883482","https://openalex.org/W2125513782","https://openalex.org/W2125965694","https://openalex.org/W2126310216","https://openalex.org/W2128620504","https://openalex.org/W2141784591","https://openalex.org/W2144021196","https://openalex.org/W2148339609","https://openalex.org/W2150441514","https://openalex.org/W2151088563","https://openalex.org/W2153317824","https://openalex.org/W2159121686","https://openalex.org/W2160823654","https://openalex.org/W2161767837","https://openalex.org/W2163578050","https://openalex.org/W2164815137"],"related_works":["https://openalex.org/W3003341543","https://openalex.org/W2049762404","https://openalex.org/W2888406770","https://openalex.org/W2369589212","https://openalex.org/W2109895582","https://openalex.org/W1590106772","https://openalex.org/W2035482730","https://openalex.org/W2049244319","https://openalex.org/W1589327193","https://openalex.org/W2036513322"],"abstract_inverted_index":{"With":[0],"the":[1,32,42,45,64,73,97,117,144],"increase":[2],"in":[3,6,31,72,126,143],"soft":[4],"failures":[5],"deep":[7],"submicron":[8],"ICs,":[9],"online":[10,24,80,119],"testing":[11,25,81],"is":[12,124],"becoming":[13],"an":[14],"integral":[15],"part":[16],"of":[17,26,37,44,66,82,91,96],"design":[18],"for":[19,23],"testability.":[20],"Some":[21],"techniques":[22],"asynchronous":[27,85],"circuits":[28],"are":[29,132],"proposed":[30],"literature,":[33],"which":[34],"involves":[35,49,89],"development":[36,90],"a":[38,92],"checker":[39,48],"that":[40],"verifies":[41],"correctness":[43],"protocol.":[46],"This":[47],"Mutex":[50],"blocks":[51],"making":[52],"its":[53],"area":[54,136],"overhead":[55],"quite":[56],"high.":[57],"In":[58],"this":[59],"paper,":[60],"we":[61],"have":[62],"adapted":[63],"Theory":[65],"Fault":[67],"Detection":[68],"and":[69,101,106,120,134],"Diagnosis":[70],"available":[71],"literature":[74],"on":[75],"Discrete":[76],"Event":[77],"Systems":[78],"to":[79,139],"speed":[83],"independent":[84],"circuits.":[86],"The":[87,114,129],"scheme":[88],"state":[93,109],"based":[94],"model":[95],"circuit,":[98],"under":[99],"normal":[100],"various":[102],"stuck-at":[103],"fault":[104],"conditions,":[105],"finally":[107],"designing":[108],"estimators":[110],"termed":[111],"as":[112],"detectors.":[113],"detectors":[115],"monitor":[116],"circuit":[118],"determine":[121],"whether":[122],"it":[123],"functioning":[125],"normal/failure":[127],"mode.":[128],"main":[130],"advantages":[131],"nonintrusiveness":[133],"low":[135],"overheads":[137],"compared":[138],"similar":[140],"schemes":[141],"reported":[142],"literature.":[145]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
