{"id":"https://openalex.org/W2084775483","doi":"https://doi.org/10.1155/2014/801241","title":"On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding","display_name":"On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding","publication_year":2014,"publication_date":"2014-05-06","ids":{"openalex":"https://openalex.org/W2084775483","doi":"https://doi.org/10.1155/2014/801241","mag":"2084775483"},"language":"en","primary_location":{"id":"doi:10.1155/2014/801241","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2014/801241","pdf_url":"https://downloads.hindawi.com/archive/2014/801241.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2014/801241.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071494100","display_name":"Khader Mohammad","orcid":"https://orcid.org/0000-0003-0047-2107"},"institutions":[{"id":"https://openalex.org/I94800806","display_name":"Birzeit University","ror":"https://ror.org/0256kw398","country_code":"PS","type":"education","lineage":["https://openalex.org/I94800806"]}],"countries":["PS"],"is_corresponding":true,"raw_author_name":"Khader Mohammad","raw_affiliation_strings":["Birzeit University, P.O. Box 14, Birzeit, West Bank, Palestine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Birzeit University, P.O. Box 14, Birzeit, West Bank, Palestine","institution_ids":["https://openalex.org/I94800806"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043139646","display_name":"Ahsan Kabeer","orcid":null},"institutions":[{"id":"https://openalex.org/I8078737","display_name":"Clemson University","ror":"https://ror.org/037s24f05","country_code":"US","type":"education","lineage":["https://openalex.org/I8078737"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ahsan Kabeer","raw_affiliation_strings":["Clemson University, Clemson, SC 29634, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Clemson University, Clemson, SC 29634, USA","institution_ids":["https://openalex.org/I8078737"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5104090957","display_name":"Tarek M. Taha","orcid":null},"institutions":[{"id":"https://openalex.org/I127591826","display_name":"University of Dayton","ror":"https://ror.org/021v3qy27","country_code":"US","type":"education","lineage":["https://openalex.org/I127591826"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tarek Taha","raw_affiliation_strings":["University of Dayton, Dayton, OH 45469, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Dayton, Dayton, OH 45469, USA","institution_ids":["https://openalex.org/I127591826"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5071494100"],"corresponding_institution_ids":["https://openalex.org/I94800806"],"apc_list":null,"apc_paid":null,"fwci":0.6216,"has_fulltext":true,"cited_by_count":8,"citation_normalized_percentile":{"value":0.73895249,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"2014","issue":null,"first_page":"1","last_page":"14"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7766404747962952},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7342875599861145},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.7064608335494995},{"id":"https://openalex.org/keywords/serialization","display_name":"Serialization","score":0.6162274479866028},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.5591927170753479},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5539129972457886},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.5418089628219604},{"id":"https://openalex.org/keywords/address-bus","display_name":"Address bus","score":0.5136842131614685},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49072539806365967},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4811645448207855},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.47324734926223755},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.47011128067970276},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45846307277679443},{"id":"https://openalex.org/keywords/local-bus","display_name":"Local bus","score":0.4562174081802368},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.44436508417129517},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.43422722816467285},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.42496585845947266},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.41404297947883606},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3915327191352844},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.3915020525455475},{"id":"https://openalex.org/keywords/control-bus","display_name":"Control bus","score":0.20866984128952026},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11948555707931519},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.065762460231781}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7766404747962952},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7342875599861145},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.7064608335494995},{"id":"https://openalex.org/C52723943","wikidata":"https://www.wikidata.org/wiki/Q1127410","display_name":"Serialization","level":2,"score":0.6162274479866028},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.5591927170753479},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5539129972457886},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.5418089628219604},{"id":"https://openalex.org/C54714250","wikidata":"https://www.wikidata.org/wiki/Q178048","display_name":"Address bus","level":3,"score":0.5136842131614685},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49072539806365967},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4811645448207855},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.47324734926223755},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.47011128067970276},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45846307277679443},{"id":"https://openalex.org/C202015219","wikidata":"https://www.wikidata.org/wiki/Q6664300","display_name":"Local bus","level":4,"score":0.4562174081802368},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.44436508417129517},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.43422722816467285},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.42496585845947266},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.41404297947883606},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3915327191352844},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3915020525455475},{"id":"https://openalex.org/C203315745","wikidata":"https://www.wikidata.org/wiki/Q2235486","display_name":"Control bus","level":3,"score":0.20866984128952026},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11948555707931519},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.065762460231781}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2014/801241","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2014/801241","pdf_url":"https://downloads.hindawi.com/archive/2014/801241.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2014/801241","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2014/801241","pdf_url":"https://downloads.hindawi.com/archive/2014/801241.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2084775483.pdf","grobid_xml":"https://content.openalex.org/works/W2084775483.grobid-xml"},"referenced_works_count":48,"referenced_works":["https://openalex.org/W361445374","https://openalex.org/W1569851653","https://openalex.org/W1829939590","https://openalex.org/W1858767651","https://openalex.org/W1951131739","https://openalex.org/W1974505834","https://openalex.org/W1989783841","https://openalex.org/W2002971900","https://openalex.org/W2008374688","https://openalex.org/W2028362246","https://openalex.org/W2032254690","https://openalex.org/W2037635237","https://openalex.org/W2069070867","https://openalex.org/W2097065626","https://openalex.org/W2100466074","https://openalex.org/W2104593972","https://openalex.org/W2106955035","https://openalex.org/W2107165052","https://openalex.org/W2108543670","https://openalex.org/W2110113956","https://openalex.org/W2111900663","https://openalex.org/W2114118161","https://openalex.org/W2117285153","https://openalex.org/W2119210197","https://openalex.org/W2123165026","https://openalex.org/W2123718082","https://openalex.org/W2124261375","https://openalex.org/W2124489208","https://openalex.org/W2127847184","https://openalex.org/W2128341608","https://openalex.org/W2138901027","https://openalex.org/W2141421397","https://openalex.org/W2142992648","https://openalex.org/W2145941625","https://openalex.org/W2148415652","https://openalex.org/W2151501490","https://openalex.org/W2152581250","https://openalex.org/W2152848860","https://openalex.org/W2156923685","https://openalex.org/W2160424446","https://openalex.org/W2160869195","https://openalex.org/W2161280215","https://openalex.org/W2164860816","https://openalex.org/W2165072326","https://openalex.org/W2165178323","https://openalex.org/W2169400452","https://openalex.org/W2171977658","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W4312759433","https://openalex.org/W273173017","https://openalex.org/W2165666031","https://openalex.org/W2166675154","https://openalex.org/W2184371594","https://openalex.org/W2464881933","https://openalex.org/W2152423944","https://openalex.org/W4321259568","https://openalex.org/W2154638254","https://openalex.org/W2027918752"],"abstract_inverted_index":{"In":[0,122],"chip-multiprocessors":[1],"(CMP)":[2],"architecture,":[3],"the":[4,10,27,44,49,56,65,68,72,91,101,113,117,136,142,148,158,170],"L2":[5,46],"cache":[6,12,29,47,51,150],"is":[7,97,120,139],"shared":[8],"by":[9],"L1":[11],"of":[13,22,40,52,67,71,90,127],"each":[14],"processor":[15],"core,":[16],"resulting":[17],"in":[18,182],"a":[19,37,77,124,177],"high":[20],"volume":[21],"diverse":[23],"data":[24,41,74,81,128,151,180],"transfer":[25,42],"through":[26,55],"L1-L2":[28],"bus.":[30,61,152],"High-performance":[31],"CMP":[32],"and":[33,48,104],"SoC":[34],"systems":[35],"have":[36],"significant":[38],"amount":[39],"between":[43],"on-chip":[45,73,118,149],"L3":[50],"off-chip":[53,59],"memory":[54,60,80],"power":[57,83,94,114,144,167],"expensive":[58],"This":[62],"paper":[63],"addresses":[64],"problem":[66],"high-power":[69],"consumption":[70,84,115],"buses,":[75],"exploring":[76],"framework":[78],"for":[79,111,116,147,173],"bus":[82,93,119,129,172,181],"minimization":[85,95],"approach.":[86],"A":[87,108],"comprehensive":[88],"analysis":[89],"existing":[92],"approaches":[96,110],"provided":[98],"based":[99],"on":[100],"performance,":[102],"power,":[103],"area":[105],"overhead":[106],"consideration.":[107],"novel":[109],"reducing":[112],"introduced.":[121],"particular,":[123],"serialization-widening":[125],"(SW)":[126],"with":[130,161],"frequent":[131],"value":[132],"encoding":[133],"(FVE),":[134],"called":[135],"SWE":[137,159],"approach,":[138],"proposed":[140],"as":[141],"best":[143],"savings":[145,168],"approach":[146,160],"The":[153],"experimental":[154],"results":[155],"show":[156],"that":[157],"FVE":[162],"can":[163],"achieve":[164],"approximately":[165],"54%":[166],"over":[169],"conventional":[171],"multicore":[174],"applications":[175],"using":[176],"64-bit":[178],"wide":[179],"45":[183],"nm":[184],"technology.":[185]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
