{"id":"https://openalex.org/W1982635493","doi":"https://doi.org/10.1155/2014/280701","title":"Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool","display_name":"Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool","publication_year":2014,"publication_date":"2014-07-24","ids":{"openalex":"https://openalex.org/W1982635493","doi":"https://doi.org/10.1155/2014/280701","mag":"1982635493"},"language":"en","primary_location":{"id":"doi:10.1155/2014/280701","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2014/280701","pdf_url":null,"source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1155/2014/280701","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082888124","display_name":"Deepa Yagain","orcid":"https://orcid.org/0000-0003-2024-6297"},"institutions":[{"id":"https://openalex.org/I196608512","display_name":"PES University","ror":"https://ror.org/05m169e78","country_code":"IN","type":"education","lineage":["https://openalex.org/I196608512"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Deepa Yagain","raw_affiliation_strings":["Department of ECE, PESIT, Bangalore 560085, India"],"raw_orcid":"https://orcid.org/0000-0003-2024-6297","affiliations":[{"raw_affiliation_string":"Department of ECE, PESIT, Bangalore 560085, India","institution_ids":["https://openalex.org/I196608512"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073396979","display_name":"Adithya Krishna","orcid":"https://orcid.org/0000-0001-9230-4068"},"institutions":[{"id":"https://openalex.org/I196608512","display_name":"PES University","ror":"https://ror.org/05m169e78","country_code":"IN","type":"education","lineage":["https://openalex.org/I196608512"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Vijaya Krishna","raw_affiliation_strings":["Department of ECE, PESIT, Bangalore 560085, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, PESIT, Bangalore 560085, India","institution_ids":["https://openalex.org/I196608512"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5082888124"],"corresponding_institution_ids":["https://openalex.org/I196608512"],"apc_list":null,"apc_paid":null,"fwci":0.5886,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.65272945,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"2014","issue":null,"first_page":"1","last_page":"18"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.9772573709487915},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6520373821258545},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.634815514087677},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5818862915039062},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5420783758163452},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5173682570457458},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5164632797241211},{"id":"https://openalex.org/keywords/transformation","display_name":"Transformation (genetics)","score":0.5137535333633423},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5096373558044434},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5051808953285217},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5036112666130066},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4707651138305664},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.4335533082485199},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41493427753448486},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21286383271217346},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16958588361740112}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.9772573709487915},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6520373821258545},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.634815514087677},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5818862915039062},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5420783758163452},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5173682570457458},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5164632797241211},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.5137535333633423},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5096373558044434},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5051808953285217},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5036112666130066},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4707651138305664},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.4335533082485199},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41493427753448486},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21286383271217346},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16958588361740112},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2014/280701","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2014/280701","pdf_url":null,"source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2014/280701","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2014/280701","pdf_url":null,"source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W123939263","https://openalex.org/W1501488688","https://openalex.org/W1984491986","https://openalex.org/W1996350869","https://openalex.org/W2001254103","https://openalex.org/W2010187744","https://openalex.org/W2017679534","https://openalex.org/W2024621293","https://openalex.org/W2040228209","https://openalex.org/W2041132958","https://openalex.org/W2057162062","https://openalex.org/W2062530062","https://openalex.org/W2074224805","https://openalex.org/W2087432294","https://openalex.org/W2087656024","https://openalex.org/W2096782987","https://openalex.org/W2099181277","https://openalex.org/W2102712964","https://openalex.org/W2106282646","https://openalex.org/W2109069558","https://openalex.org/W2114967122","https://openalex.org/W2140439614","https://openalex.org/W2140960395","https://openalex.org/W2146142332"],"related_works":["https://openalex.org/W2310025803","https://openalex.org/W2067951144","https://openalex.org/W1593777258","https://openalex.org/W2040758634","https://openalex.org/W601035816","https://openalex.org/W2086920137","https://openalex.org/W2023505575","https://openalex.org/W2392961650","https://openalex.org/W3124471820","https://openalex.org/W1982635493"],"abstract_inverted_index":{"Retiming":[0],"is":[1,35,44,111,135,142,152],"a":[2,92,136],"transformation":[3,19,52,78],"which":[4,54,134],"can":[5,13,120],"be":[6,121],"applied":[7],"to":[8,46,180],"digital":[9,175],"filter":[10,116,146,176],"blocks":[11,49,101],"that":[12,154],"increase":[14],"the":[15,59,67,71,130],"clock":[16],"frequency.":[17,165],"This":[18,119,166],"requires":[20],"computation":[21,60],"of":[22,58,69,73,84,163],"critical":[23],"path":[24,27,47,74,85],"and":[25,91,105,188],"shortest":[26],"at":[28,37],"various":[29,170],"stages.":[30],"In":[31,62,129],"literature,":[32],"this":[33,63],"problem":[34,68],"addressed":[36],"multiple":[38],"points.":[39],"However,":[40],"very":[41,112],"little":[42],"attention":[43],"given":[45],"solver":[48,86],"in":[50,76,161],"retiming":[51,77,133,155,171],"algorithm":[53,87],"takes":[55],"up":[56],"most":[57],"time.":[61],"paper,":[64],"we":[65],"address":[66],"optimizing":[70],"speed":[72],"solvers":[75],"by":[79,124],"introducing":[80],"high":[81,137],"level":[82,138],"synthesis":[83,139],"architectures":[88],"on":[89],"FPGA":[90],"computer":[93],"aided":[94],"design":[95,177],"tool.":[96],"Filters":[97],"have":[98],"their":[99],"combination":[100],"as":[102,185],"adders,":[103],"multipliers,":[104],"delay":[106],"elements.":[107],"Avoiding":[108],"costly":[109],"multipliers":[110],"much":[113],"needed":[114],"for":[115,173],"hardware":[117],"implementation.":[118],"achieved":[122],"efficiently":[123],"using":[125,148],"multiplierless":[126,145,156,174],"MCM":[127,149],"technique.":[128],"present":[131],"work,":[132],"optimization":[140],"method":[141],"combined":[143],"with":[144,178],"implementations":[147],"algorithm.":[150],"It":[151],"seen":[153],"designs":[157],"gives":[158],"better":[159],"performance":[160,182],"terms":[162],"operating":[164],"paper":[167],"also":[168],"compares":[169],"techniques":[172],"respect":[179],"VLSI":[181],"metrics":[183],"such":[184],"area,":[186],"speed,":[187],"power.":[189]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}