{"id":"https://openalex.org/W1989491630","doi":"https://doi.org/10.1155/2013/936181","title":"Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration","display_name":"Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration","publication_year":2013,"publication_date":"2013-07-11","ids":{"openalex":"https://openalex.org/W1989491630","doi":"https://doi.org/10.1155/2013/936181","mag":"1989491630"},"language":"en","primary_location":{"id":"doi:10.1155/2013/936181","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2013/936181","pdf_url":"https://downloads.hindawi.com/archive/2013/936181.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2013/936181.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042753361","display_name":"Bisrat Tafesse","orcid":null},"institutions":[{"id":"https://openalex.org/I133999245","display_name":"University of Nevada, Las Vegas","ror":"https://ror.org/0406gha72","country_code":"US","type":"education","lineage":["https://openalex.org/I133999245"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Bisrat Tafesse","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Nevada Las Vegas, 4505 Maryland Pkwy, Las Vegas, NV 89154, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Nevada Las Vegas, 4505 Maryland Pkwy, Las Vegas, NV 89154, USA","institution_ids":["https://openalex.org/I133999245"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069307987","display_name":"Venkatesan Muthukumar","orcid":"https://orcid.org/0000-0001-5357-5500"},"institutions":[{"id":"https://openalex.org/I133999245","display_name":"University of Nevada, Las Vegas","ror":"https://ror.org/0406gha72","country_code":"US","type":"education","lineage":["https://openalex.org/I133999245"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Venkatesan Muthukumar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Nevada Las Vegas, 4505 Maryland Pkwy, Las Vegas, NV 89154, USA"],"raw_orcid":"https://orcid.org/0000-0001-5357-5500","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Nevada Las Vegas, 4505 Maryland Pkwy, Las Vegas, NV 89154, USA","institution_ids":["https://openalex.org/I133999245"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5042753361"],"corresponding_institution_ids":["https://openalex.org/I133999245"],"apc_list":null,"apc_paid":null,"fwci":1.8856,"has_fulltext":true,"cited_by_count":9,"citation_normalized_percentile":{"value":0.86780596,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"2013","issue":null,"first_page":"1","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8971999883651733},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7981626987457275},{"id":"https://openalex.org/keywords/uniprocessor-system","display_name":"Uniprocessor system","score":0.7924549579620361},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7582169771194458},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6967796087265015},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.5761584639549255},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.553587794303894},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.5291255712509155},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.46226751804351807},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4256581664085388},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.373690128326416},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3716033101081848},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09137243032455444}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8971999883651733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7981626987457275},{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.7924549579620361},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7582169771194458},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6967796087265015},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.5761584639549255},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.553587794303894},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.5291255712509155},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.46226751804351807},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4256581664085388},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.373690128326416},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3716033101081848},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09137243032455444},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1155/2013/936181","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2013/936181","pdf_url":"https://downloads.hindawi.com/archive/2013/936181.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:digitalscholarship.unlv.edu:ece_fac_articles-1747","is_oa":false,"landing_page_url":"https://digitalscholarship.unlv.edu/ece_fac_articles/746","pdf_url":null,"source":{"id":"https://openalex.org/S4377196371","display_name":"Digital Scholarship - UNLV (University of Nevada Reno)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I134113660","host_organization_name":"University of Nevada, Reno","host_organization_lineage":["https://openalex.org/I134113660"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical and Computer Engineering Faculty Publications","raw_type":"text"},{"id":"pmh:oai:oasis.library.unlv.edu:ece_fac_articles-1747","is_oa":true,"landing_page_url":"https://oasis.library.unlv.edu/ece_fac_articles/746","pdf_url":null,"source":{"id":"https://openalex.org/S4377196371","display_name":"Digital Scholarship - UNLV (University of Nevada Reno)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I134113660","host_organization_name":"University of Nevada, Reno","host_organization_lineage":["https://openalex.org/I134113660"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical & Computer Engineering Faculty Research","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2013/936181","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2013/936181","pdf_url":"https://downloads.hindawi.com/archive/2013/936181.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1989491630.pdf","grobid_xml":"https://content.openalex.org/works/W1989491630.grobid-xml"},"referenced_works_count":54,"referenced_works":["https://openalex.org/W34673359","https://openalex.org/W1544708329","https://openalex.org/W1580327099","https://openalex.org/W1968432533","https://openalex.org/W1971010734","https://openalex.org/W1975329204","https://openalex.org/W2003080753","https://openalex.org/W2006800740","https://openalex.org/W2012973690","https://openalex.org/W2022673945","https://openalex.org/W2034984722","https://openalex.org/W2035186408","https://openalex.org/W2038884827","https://openalex.org/W2055649415","https://openalex.org/W2069573248","https://openalex.org/W2077217834","https://openalex.org/W2082921355","https://openalex.org/W2086708153","https://openalex.org/W2090190382","https://openalex.org/W2099270353","https://openalex.org/W2101183260","https://openalex.org/W2105131265","https://openalex.org/W2107212752","https://openalex.org/W2108436158","https://openalex.org/W2111134965","https://openalex.org/W2111893839","https://openalex.org/W2113968888","https://openalex.org/W2117675075","https://openalex.org/W2117701224","https://openalex.org/W2122586531","https://openalex.org/W2122593349","https://openalex.org/W2126349935","https://openalex.org/W2127318527","https://openalex.org/W2127430446","https://openalex.org/W2135733703","https://openalex.org/W2138177821","https://openalex.org/W2141721356","https://openalex.org/W2147446937","https://openalex.org/W2147915525","https://openalex.org/W2148897044","https://openalex.org/W2149935279","https://openalex.org/W2150550920","https://openalex.org/W2152801763","https://openalex.org/W2153625096","https://openalex.org/W2155484663","https://openalex.org/W2156475585","https://openalex.org/W2158051804","https://openalex.org/W2160847478","https://openalex.org/W2161350011","https://openalex.org/W2163590199","https://openalex.org/W2171215895","https://openalex.org/W2171595125","https://openalex.org/W2341350247","https://openalex.org/W3000384474"],"related_works":["https://openalex.org/W1934552808","https://openalex.org/W3198758847","https://openalex.org/W2587830891","https://openalex.org/W4230458348","https://openalex.org/W2119904701","https://openalex.org/W4234221021","https://openalex.org/W2106200299","https://openalex.org/W2178653557","https://openalex.org/W1989491630","https://openalex.org/W2884668617"],"abstract_inverted_index":{"Due":[0],"to":[1,15,45,98,103],"the":[2,17,49,86,119,148,173,178],"ever-growing":[3],"requirements":[4],"in":[5,19,42,90],"high":[6],"performance":[7],"data":[8],"computation,":[9],"multiprocessor":[10,24,91,110,135,186],"systems":[11,25],"have":[12],"been":[13],"proposed":[14,169],"solve":[16],"bottlenecks":[18],"uniprocessor":[20],"systems.":[21,111],"Developing":[22,69],"efficient":[23,70],"requires":[26],"effective":[27],"exploration":[28,120],"of":[29,51,58,67,123,177],"design":[30,125,179,194,213],"choices":[31],"like":[32],"application":[33,166],"scheduling,":[34,75],"mapping,":[35],"and":[36,76,105,121,138,161,198,209],"architecture":[37],"design.":[38],"Also,":[39],"fault":[40],"tolerance":[41],"multiprocessors":[43,59],"needs":[44],"be":[46],"addressed.":[47],"With":[48],"advent":[50],"nanometer-process":[52],"technology":[53],"for":[54,79,118,127,141,164,183,211],"chip":[55],"manufacturing,":[56],"realization":[57],"on":[60,109],"SoC":[61],"(MpSoC)":[62],"is":[63],"an":[64],"active":[65],"field":[66],"research.":[68],"low":[71],"power,":[72],"fault-tolerant":[73,158],"task":[74,136,202],"mapping":[77,139,162],"techniques":[78],"MpSoCs":[80],"require":[81],"optimized":[82],"algorithms":[83,108,126,140,144,170],"that":[84],"consider":[85,171],"various":[87,124,212],"scenarios":[88],"inherent":[89],"environments.":[92],"Therefore":[93],"there":[94],"exists":[95],"a":[96,100,115,156,184],"need":[97],"develop":[99],"simulation":[101,150,187],"framework":[102,117,182],"explore":[104],"evaluate":[106],"new":[107,134],"This":[112,130],"work":[113,131],"proposes":[114,133,155],"modular":[116],"evaluation":[122,205],"MpSoC":[128],"system.":[129],"also":[132,154],"scheduling":[137,160],"MpSoCs.":[142],"These":[143],"are":[145,207],"evaluated":[146,199,208],"using":[147,190,200],"developed":[149,189],"framework.":[151],"The":[152,168,181],"paper":[153],"dynamic":[157],"(FT)":[159],"algorithm":[163],"robust":[165],"processing.":[167],"optimizing":[172],"power":[174],"as":[175],"one":[176],"constraints.":[180],"heterogeneous":[185],"was":[188],"SystemC/C++":[191],"language.":[192],"Various":[193],"variations":[195],"were":[196],"implemented":[197],"standard":[201],"graphs.":[203],"Performance":[204],"metrics":[206],"discussed":[210],"scenarios.":[214]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}