{"id":"https://openalex.org/W2004756474","doi":"https://doi.org/10.1155/2013/529150","title":"A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation","display_name":"A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation","publication_year":2013,"publication_date":"2013-05-16","ids":{"openalex":"https://openalex.org/W2004756474","doi":"https://doi.org/10.1155/2013/529150","mag":"2004756474"},"language":"en","primary_location":{"id":"doi:10.1155/2013/529150","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2013/529150","pdf_url":"https://downloads.hindawi.com/archive/2013/529150.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2013/529150.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064022627","display_name":"Ching-Lung Su","orcid":null},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Lung Su","raw_affiliation_strings":["Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin 640, Taiwan","Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin 640, Taiwan","institution_ids":["https://openalex.org/I75357094"]},{"raw_affiliation_string":"Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin, Taiwan#TAB#","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005176613","display_name":"Tse-Min Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Tse-Min Chen","raw_affiliation_strings":["Graduate School of Engineering Science and Technology, National Yunlin University of Science Technology, Yun-Lin 640, Taiwan","Graduate School of Engineering Science and Technology, National Yunlin University of Science Technology, Yun-Lin, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Engineering Science and Technology, National Yunlin University of Science Technology, Yun-Lin 640, Taiwan","institution_ids":["https://openalex.org/I75357094"]},{"raw_affiliation_string":"Graduate School of Engineering Science and Technology, National Yunlin University of Science Technology, Yun-Lin, Taiwan#TAB#","institution_ids":["https://openalex.org/I75357094"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069903658","display_name":"Kuo-Hsuan Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I75357094","display_name":"National Yunlin University of Science and Technology","ror":"https://ror.org/04qkq2m54","country_code":"TW","type":"education","lineage":["https://openalex.org/I75357094"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kuo-Hsuan Wu","raw_affiliation_strings":["Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin 640, Taiwan","Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin, Taiwan#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin 640, Taiwan","institution_ids":["https://openalex.org/I75357094"]},{"raw_affiliation_string":"Department of Electronics Engineering, National Yunlin University of Science Technology, Yun-Lin, Taiwan#TAB#","institution_ids":["https://openalex.org/I75357094"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5005176613"],"corresponding_institution_ids":["https://openalex.org/I75357094"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08139535,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2013","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6183387041091919},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6088916063308716},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.5564984083175659},{"id":"https://openalex.org/keywords/estimator","display_name":"Estimator","score":0.5552729964256287},{"id":"https://openalex.org/keywords/profiling","display_name":"Profiling (computer programming)","score":0.507729172706604},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4900859594345093},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46967989206314087},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.13500627875328064}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6183387041091919},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6088916063308716},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.5564984083175659},{"id":"https://openalex.org/C185429906","wikidata":"https://www.wikidata.org/wiki/Q1130160","display_name":"Estimator","level":2,"score":0.5552729964256287},{"id":"https://openalex.org/C187191949","wikidata":"https://www.wikidata.org/wiki/Q1138496","display_name":"Profiling (computer programming)","level":2,"score":0.507729172706604},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4900859594345093},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46967989206314087},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.13500627875328064},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2013/529150","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2013/529150","pdf_url":"https://downloads.hindawi.com/archive/2013/529150.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2013/529150","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2013/529150","pdf_url":"https://downloads.hindawi.com/archive/2013/529150.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4914455285","display_name":null,"funder_award_id":"NSC 100-2221-E-224-034-MY3","funder_id":"https://openalex.org/F4320321040","funder_display_name":"National Science Council"}],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2004756474.pdf","grobid_xml":"https://content.openalex.org/works/W2004756474.grobid-xml"},"referenced_works_count":13,"referenced_works":["https://openalex.org/W1814926891","https://openalex.org/W2016837603","https://openalex.org/W2055902061","https://openalex.org/W2065051393","https://openalex.org/W2101855556","https://openalex.org/W2107920087","https://openalex.org/W2108052225","https://openalex.org/W2108376611","https://openalex.org/W2139045252","https://openalex.org/W2142094185","https://openalex.org/W2149355718","https://openalex.org/W2163596137","https://openalex.org/W2425240487"],"related_works":["https://openalex.org/W2356602486","https://openalex.org/W2351992668","https://openalex.org/W2324828474","https://openalex.org/W2374315191","https://openalex.org/W2391207559","https://openalex.org/W2384715785","https://openalex.org/W2349624418","https://openalex.org/W2064459023","https://openalex.org/W2115579119","https://openalex.org/W2017236304"],"abstract_inverted_index":{"A":[0],"prototype-based":[1],"SoC":[2,21,27,39,50,90,98,155],"performance":[3,28,43,102],"estimation":[4,109],"methodology":[5],"was":[6,103,141],"proposed":[7,108,139],"for":[8,151],"consumer":[9],"electronics":[10],"design.":[11,99],"Traditionally,":[12],"prototypes":[13,91],"are":[14],"usually":[15],"used":[16],"in":[17],"system":[18,101],"verification":[19],"before":[20],"tapeout,":[22],"which":[23,59],"is":[24],"without":[25],"accurate":[26],"exploration":[29],"and":[30,45,75,85,121],"estimation.":[31],"This":[32],"paper":[33],"attempted":[34],"to":[35,94,106],"carefully":[36],"model":[37,95],"the":[38,47,55,61,86,107,111,115,122,126,130,138],"prototype":[40,53,79],"as":[41],"a":[42,96],"estimator":[44],"explore":[46],"environment":[48],"of":[49,63,89,114,129,147,149],"performance.":[51],"The":[52,78,100,133],"met":[54],"gate-level":[56],"cycle-accurate":[57],"requirement,":[58],"covered":[60],"effect":[62],"embedded":[64,71],"processor,":[65],"on-chip":[66],"bus":[67],"structure,":[68],"IP":[69],"design,":[70],"OS,":[72],"GUI":[73],"systems,":[74],"application":[76,116],"programs.":[77],"configuration,":[80],"chip":[81],"post-layout":[82,127],"simulation":[83,128],"result,":[84],"measured":[87],"parameters":[88,124],"were":[92],"merged":[93],"target":[97,131],"examined":[104],"according":[105],"models,":[110],"profiling":[112],"result":[113,135],"programs":[117],"ported":[118],"on":[119],"prototypes,":[120],"timing":[123],"from":[125],"SoC.":[132],"experimental":[134],"showed":[136],"that":[137],"method":[140],"accompanied":[142],"with":[143],"only":[144],"an":[145,152],"average":[146],"2.08%":[148],"error":[150],"MPEG-4":[153],"decoder":[154],"at":[156],"simple":[157],"profile":[158],"level":[159],"2":[160],"specifications.":[161]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
