{"id":"https://openalex.org/W2064024864","doi":"https://doi.org/10.1155/2012/580584","title":"Enabling Fast ASIP Design Space Exploration: An FPGA\u2010Based Runtime Reconfigurable Prototyper","display_name":"Enabling Fast ASIP Design Space Exploration: An FPGA\u2010Based Runtime Reconfigurable Prototyper","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W2064024864","doi":"https://doi.org/10.1155/2012/580584","mag":"2064024864"},"language":"en","primary_location":{"id":"doi:10.1155/2012/580584","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/580584","pdf_url":"https://downloads.hindawi.com/archive/2012/580584.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2012/580584.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050421874","display_name":"Paolo Meloni","orcid":"https://orcid.org/0000-0002-8106-4641"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Paolo Meloni","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000070335","display_name":"Sebastiano Pomata","orcid":null},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Sebastiano Pomata","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034689390","display_name":"Giuseppe Tuveri","orcid":null},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giuseppe Tuveri","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081406299","display_name":"Simone Secchi","orcid":"https://orcid.org/0000-0002-8539-1578"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Simone Secchi","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007761671","display_name":"Luigi Raffo","orcid":"https://orcid.org/0000-0001-9683-009X"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luigi Raffo","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Dept. of Electrical and Electronic Engineering, Univ. of Cagliari, Cagliari, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091764184","display_name":"Menno Lindwer","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Menno Lindwer","raw_affiliation_strings":["Silicon Hive B.V., High Tech Campus, 5656AE Eindhoven, The Netherlands","Silicon Hive B.V., Eindhoven, The Netherlands#TAB#"],"affiliations":[{"raw_affiliation_string":"Silicon Hive B.V., High Tech Campus, 5656AE Eindhoven, The Netherlands","institution_ids":[]},{"raw_affiliation_string":"Silicon Hive B.V., Eindhoven, The Netherlands#TAB#","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5050421874"],"corresponding_institution_ids":["https://openalex.org/I172446870"],"apc_list":null,"apc_paid":null,"fwci":2.3422,"has_fulltext":true,"cited_by_count":13,"citation_normalized_percentile":{"value":0.88368307,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"2012","issue":"1","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8386570811271667},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7150806188583374},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6109282374382019},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5679029226303101},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.45980918407440186},{"id":"https://openalex.org/keywords/space","display_name":"Space (punctuation)","score":0.4210909903049469},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38664132356643677},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3315391540527344},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13784652948379517}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8386570811271667},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7150806188583374},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6109282374382019},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5679029226303101},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.45980918407440186},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.4210909903049469},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38664132356643677},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3315391540527344},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13784652948379517}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/2012/580584","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/580584","pdf_url":"https://downloads.hindawi.com/archive/2012/580584.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:iris.unica.it:11584/99082","is_oa":true,"landing_page_url":"http://hdl.handle.net/11584/99082","pdf_url":"http://www.hindawi.com/journals/vlsi/2012/580584/","source":{"id":"https://openalex.org/S4377196293","display_name":"UNICA IRIS Institutional Research Information System (University of Cagliari)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172446870","host_organization_name":"University of Cagliari","host_organization_lineage":["https://openalex.org/I172446870"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"doi:10.1155/2012/580584","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/580584","pdf_url":"https://downloads.hindawi.com/archive/2012/580584.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G241697444","display_name":null,"funder_award_id":"248424","funder_id":"https://openalex.org/F4320333065","funder_display_name":"Seventh Framework Programme"},{"id":"https://openalex.org/G4481566865","display_name":null,"funder_award_id":"PO Sardegna FSE 2007-2013","funder_id":"https://openalex.org/F4320326069","funder_display_name":"Regione Autonoma della Sardegna"},{"id":"https://openalex.org/G5106973695","display_name":null,"funder_award_id":"L.R.7/2007","funder_id":"https://openalex.org/F4320326069","funder_display_name":"Regione Autonoma della Sardegna"},{"id":"https://openalex.org/G5533836038","display_name":null,"funder_award_id":"FSE 2007-2013","funder_id":"https://openalex.org/F4320326069","funder_display_name":"Regione Autonoma della Sardegna"},{"id":"https://openalex.org/G907008408","display_name":null,"funder_award_id":"7/2007","funder_id":"https://openalex.org/F4320326069","funder_display_name":"Regione Autonoma della Sardegna"}],"funders":[{"id":"https://openalex.org/F4320326069","display_name":"Regione Autonoma della Sardegna","ror":null},{"id":"https://openalex.org/F4320333065","display_name":"Seventh Framework Programme","ror":null}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2064024864.pdf","grobid_xml":"https://content.openalex.org/works/W2064024864.grobid-xml"},"referenced_works_count":29,"referenced_works":["https://openalex.org/W1540027087","https://openalex.org/W1553214226","https://openalex.org/W1861759238","https://openalex.org/W1965372861","https://openalex.org/W1970939331","https://openalex.org/W1983899098","https://openalex.org/W1991849527","https://openalex.org/W2021977801","https://openalex.org/W2042041356","https://openalex.org/W2066339098","https://openalex.org/W2103127274","https://openalex.org/W2104225326","https://openalex.org/W2108321287","https://openalex.org/W2108827571","https://openalex.org/W2120635877","https://openalex.org/W2123715095","https://openalex.org/W2124495571","https://openalex.org/W2134470641","https://openalex.org/W2136084694","https://openalex.org/W2147657366","https://openalex.org/W2152886964","https://openalex.org/W2161522487","https://openalex.org/W2166197680","https://openalex.org/W2167985917","https://openalex.org/W2996989811","https://openalex.org/W3137094666","https://openalex.org/W3148322066","https://openalex.org/W4233530951","https://openalex.org/W4251534053"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2111062328","https://openalex.org/W4313341326","https://openalex.org/W2108386578","https://openalex.org/W1572417577","https://openalex.org/W91363257","https://openalex.org/W2142450926","https://openalex.org/W3139655666"],"abstract_inverted_index":{"Application":[0],"Specific":[1],"Instruction\u2010set":[2],"Processors":[3],"(ASIPs)":[4],"expose":[5],"to":[6,23,40,63,69,157],"the":[7,25,46,54,57,121,146,167,170,175,188],"designer":[8],"a":[9,84,93,99,137],"large":[10],"number":[11],"of":[12,14,48,56,86,101,112,169,197],"degrees":[13],"freedom.":[15],"Accurate":[16],"and":[17,106,140,160,191],"rapid":[18],"simulation":[19],"tools":[20],"are":[21,51],"needed":[22],"explore":[24],"design":[26,122,176],"space.":[27],"To":[28],"this":[29,76,81],"aim,":[30],"FPGA\u2010based":[31],"emulators":[32],"have":[33],"recently":[34],"been":[35,130],"proposed":[36],"as":[37],"an":[38,108,141,182],"alternative":[39],"pure":[41],"software":[42,116],"cycle\u2010accurate":[43],"simulator.":[44],"However,":[45],"advantages":[47],"on\u2010hardware":[49],"emulation":[50,95,148,152],"reduced":[52],"by":[53],"overhead":[55,183],"RTL":[58],"synthesis":[59],"process":[60],"that":[61],"needs":[62],"be":[64,70],"run":[65],"for":[66,187],"each":[67],"configuration":[68],"emulated.":[71],"The":[72,127],"work":[73],"presented":[74,147,171],"in":[75,195],"paper":[77],"aims":[78],"at":[79,117],"mitigating":[80],"overhead,":[82],"exploiting":[83],"form":[85],"software\u2010driven":[87],"platform":[88],"runtime":[89],"reconfiguration.":[90],"We":[91,164],"present":[92],"complete":[94],"toolchain":[96,149,172],"that,":[97],"given":[98],"set":[100],"candidate":[102],"ASIP":[103],"configurations,":[104],"identifies":[105],"builds":[107],"overdimensioned":[109],"architecture":[110],"capable":[111],"being":[113],"reconfigured":[114],"via":[115],"runtime,":[118],"emulating":[119],"all":[120],"space":[123,177],"points":[124],"under":[125],"evaluation.":[126],"approach":[128],"has":[129],"validated":[131],"against":[132],"two":[133],"different":[134],"case":[135],"studies,":[136],"filtering":[138],"kernel":[139],"M\u2010JPEG":[142],"encoding":[143],"kernel.":[144],"Moreover,":[145],"couples":[150],"FPGA":[151,189],"with":[153],"activity\u2010based":[154],"physical":[155],"modeling":[156],"extract":[158],"area":[159],"power/energy":[161],"consumption":[162],"figures.":[163],"show":[165],"how":[166],"adoption":[168],"reduces":[173],"significantly":[174],"exploration":[178],"time,":[179],"while":[180],"introducing":[181],"lower":[184,192],"than":[185,193],"10%":[186],"resources":[190],"0.5%":[194],"terms":[196],"operating":[198],"frequency.":[199]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}