{"id":"https://openalex.org/W1986774178","doi":"https://doi.org/10.1155/2012/575389","title":"Redundant Logic Insertion and Latency Reduction in Self\u2010Timed Adders","display_name":"Redundant Logic Insertion and Latency Reduction in Self\u2010Timed Adders","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W1986774178","doi":"https://doi.org/10.1155/2012/575389","mag":"1986774178"},"language":"en","primary_location":{"id":"doi:10.1155/2012/575389","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/575389","pdf_url":"https://downloads.hindawi.com/archive/2012/575389.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2012/575389.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112390368","display_name":"P. Balasubramanian","orcid":null},"institutions":[{"id":"https://openalex.org/I1330855593","display_name":"Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology","ror":"https://ror.org/05bc5bx80","country_code":"IN","type":"education","lineage":["https://openalex.org/I1330855593"]},{"id":"https://openalex.org/I33585257","display_name":"Anna University, Chennai","ror":"https://ror.org/01qhf1r47","country_code":"IN","type":"education","lineage":["https://openalex.org/I33585257"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"P. Balasubramanian","raw_affiliation_strings":["Department of Electronics and Communication Engineering, S.A. Engineering College, Anna University, Thiruverkadu, Tamil Nadu, Chennai 600 077, India","Department of Electronics and Communication Engineering, Vel Tech Dr. RR and Dr. SR Technical University, Avadi,  Tamil Nadu, Chennai 600 062, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, S.A. Engineering College, Anna University, Thiruverkadu, Tamil Nadu, Chennai 600 077, India","institution_ids":["https://openalex.org/I33585257"]},{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Vel Tech Dr. RR and Dr. SR Technical University, Avadi,  Tamil Nadu, Chennai 600 062, India","institution_ids":["https://openalex.org/I1330855593"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108435403","display_name":"D. Edwards","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D. A. Edwards","raw_affiliation_strings":["School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038432274","display_name":"William Toms","orcid":"https://orcid.org/0000-0002-8126-4993"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"W. B. Toms","raw_affiliation_strings":["School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, UK"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5112390368"],"corresponding_institution_ids":["https://openalex.org/I1330855593","https://openalex.org/I33585257"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":21,"citation_normalized_percentile":{"value":0.07149371,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"2012","issue":"1","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6863657236099243},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6800732612609863},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6300133466720581},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6065105199813843},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4955052137374878},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.374656617641449},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3243643641471863},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.320664644241333},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20454475283622742},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11287501454353333}],"concepts":[{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6863657236099243},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6800732612609863},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6300133466720581},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6065105199813843},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4955052137374878},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.374656617641449},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3243643641471863},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.320664644241333},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20454475283622742},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11287501454353333},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1155/2012/575389","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/575389","pdf_url":"https://downloads.hindawi.com/archive/2012/575389.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/c8d4fda4-cd75-41ae-b81f-5cf7adc6610a","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/c8d4fda4-cd75-41ae-b81f-5cf7adc6610a","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Balasubramanian, P, Edwards, D A & Toms, W B 2012, 'Redundant logic insertion and latency reduction in self-timed adders', VLSI Design, vol. 2012, 575389. https://doi.org/10.1155/2012/575389","raw_type":"article"},{"id":"pmh:oai:pure.atira.dk:publications/c8d4fda4-cd75-41ae-b81f-5cf7adc6610a","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=84862275094&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Balasubramanian, P, Edwards, D A & Toms, W B 2012, 'Redundant logic insertion and latency reduction in self-timed adders', VLSI Design, vol. 2012, 575389. https://doi.org/10.1155/2012/575389","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2012/575389","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/575389","pdf_url":"https://downloads.hindawi.com/archive/2012/575389.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1934935867","display_name":null,"funder_award_id":"Engineering and Physical Sciences R","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5659856733","display_name":"SElf-timed DATapath synthEsis (SEDATE)","funder_award_id":"EP/D052238/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5898281676","display_name":null,"funder_award_id":"EP/G02930X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G661603445","display_name":null,"funder_award_id":"EP/D052238/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320320291","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1986774178.pdf","grobid_xml":"https://content.openalex.org/works/W1986774178.grobid-xml"},"referenced_works_count":35,"referenced_works":["https://openalex.org/W1483902580","https://openalex.org/W1509814569","https://openalex.org/W1513324186","https://openalex.org/W1522009072","https://openalex.org/W1535891768","https://openalex.org/W1967575124","https://openalex.org/W1996902351","https://openalex.org/W1999082644","https://openalex.org/W2021330840","https://openalex.org/W2041997887","https://openalex.org/W2042479232","https://openalex.org/W2051380786","https://openalex.org/W2052771421","https://openalex.org/W2059456074","https://openalex.org/W2060903533","https://openalex.org/W2064133784","https://openalex.org/W2073561588","https://openalex.org/W2102279524","https://openalex.org/W2102346142","https://openalex.org/W2107103004","https://openalex.org/W2107369380","https://openalex.org/W2113505496","https://openalex.org/W2127220676","https://openalex.org/W2134829921","https://openalex.org/W2139882509","https://openalex.org/W2145973680","https://openalex.org/W2150872535","https://openalex.org/W2152229138","https://openalex.org/W2153257335","https://openalex.org/W2158159636","https://openalex.org/W2158520861","https://openalex.org/W2487142227","https://openalex.org/W2554051124","https://openalex.org/W2911717499","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W1993041309","https://openalex.org/W2013839957","https://openalex.org/W3196607417"],"abstract_inverted_index":{"A":[0],"novel":[1],"concept":[2,20],"of":[3,34,48,57,80,131,156],"logic":[4,39,50,102,138],"redundancy":[5],"insertion":[6],"is":[7,21],"presented":[8],"that":[9,26,67,112],"facilitates":[10],"significant":[11],"latency":[12,74,153],"reduction":[13,115],"in":[14,23,82,108,146],"self\u2010timed":[15,35,46,60],"adder":[16],"circuits.":[17],"The":[18],"proposed":[19],"universal":[22],"the":[24,54,71,78,113,141],"sense":[25],"it":[27,63,104],"can":[28,40],"be":[29,41,117],"extended":[30],"to":[31,43,93],"a":[32,58,109],"variety":[33],"design":[36],"methods.":[37],"Redundant":[38],"incorporated":[42],"generate":[44],"efficient":[45],"realizations":[47],"iterative":[49],"specifications.":[51],"Based":[52],"on":[53,90],"case":[55,152],"study":[56],"32\u2010bit":[59],"carry\u2010ripple":[61],"adder,":[62],"has":[64,105],"been":[65,106],"found":[66],"redundant":[68,137],"implementations":[69],"minimize":[70],"data":[72],"path":[73],"by":[75,86,124],"21.1%":[76],"at":[77],"expense":[79],"increases":[81],"area":[83,127],"and":[84,88,128,133,149],"power":[85,129],"2.3%":[87],"0.8%":[89],"average":[91],"compared":[92],"their":[94],"nonredundant":[95],"counterparts.":[96],"However,":[97],"when":[98],"considering":[99],"further":[100],"peephole":[101],"optimizations,":[103],"observed":[107],"specific":[110],"scenario":[111],"delay":[114],"could":[116],"as":[118,120],"high":[119],"31%":[121],"while":[122],"accompanied":[123],"only":[125],"meager":[126],"penalties":[130],"0.6%":[132],"1.2%,":[134],"respectively.":[135],"Moreover,":[136],"adders":[139],"pave":[140],"way":[142],"for":[143,154],"spacer":[144],"propagation":[145],"constant":[147],"time":[148],"garner":[150],"actual":[151],"addition":[155],"valid":[157],"data.":[158]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":3}],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-10-10T00:00:00"}
