{"id":"https://openalex.org/W2123931172","doi":"https://doi.org/10.1155/2012/546212","title":"Design of an All\u2010Digital Synchronized Frequency Multiplier Based on a Dual\u2010Loop (D/FLL) Architecture","display_name":"Design of an All\u2010Digital Synchronized Frequency Multiplier Based on a Dual\u2010Loop (D/FLL) Architecture","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W2123931172","doi":"https://doi.org/10.1155/2012/546212","mag":"2123931172"},"language":"en","primary_location":{"id":"doi:10.1155/2012/546212","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/546212","pdf_url":"https://downloads.hindawi.com/archive/2012/546212.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2012/546212.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051194064","display_name":"Maher Assaad","orcid":"https://orcid.org/0000-0002-1584-8747"},"institutions":[{"id":"https://openalex.org/I182023848","display_name":"Petronas (Malaysia)","ror":"https://ror.org/02tc7rm90","country_code":"MY","type":"company","lineage":["https://openalex.org/I182023848"]}],"countries":["MY"],"is_corresponding":true,"raw_author_name":"Maher Assaad","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, University Technology of PETRONAS (UTP), Perak, 31750 Tronoh","Department of Electrical and Electronics Engineering, University Technology of PETRONAS, Perak, Tronoh, Malaysia#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, University Technology of PETRONAS (UTP), Perak, 31750 Tronoh","institution_ids":["https://openalex.org/I182023848"]},{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, University Technology of PETRONAS, Perak, Tronoh, Malaysia#TAB#","institution_ids":["https://openalex.org/I182023848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081055664","display_name":"Mohammed Alser","orcid":"https://orcid.org/0000-0002-6117-3701"},"institutions":[{"id":"https://openalex.org/I182023848","display_name":"Petronas (Malaysia)","ror":"https://ror.org/02tc7rm90","country_code":"MY","type":"company","lineage":["https://openalex.org/I182023848"]}],"countries":["MY"],"is_corresponding":true,"raw_author_name":"Mohammed H. Alser","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, University Technology of PETRONAS (UTP), Perak, 31750 Tronoh","Department of Electrical and Electronics Engineering, University Technology of PETRONAS, Perak, Tronoh, Malaysia#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, University Technology of PETRONAS (UTP), Perak, 31750 Tronoh","institution_ids":["https://openalex.org/I182023848"]},{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, University Technology of PETRONAS, Perak, Tronoh, Malaysia#TAB#","institution_ids":["https://openalex.org/I182023848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5051194064","https://openalex.org/A5081055664"],"corresponding_institution_ids":["https://openalex.org/I182023848"],"apc_list":null,"apc_paid":null,"fwci":0.4261,"has_fulltext":true,"cited_by_count":7,"citation_normalized_percentile":{"value":0.70235429,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"2012","issue":"1","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7136066555976868},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7097722887992859},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7005226016044617},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6820825338363647},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6332977414131165},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5992488265037537},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4949294924736023},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4634897708892822},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.4530212879180908},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44670307636260986},{"id":"https://openalex.org/keywords/frequency-multiplier","display_name":"Frequency multiplier","score":0.41728657484054565},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.315234512090683},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.2762256860733032},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22817984223365784},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08888527750968933}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7136066555976868},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7097722887992859},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7005226016044617},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6820825338363647},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6332977414131165},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5992488265037537},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4949294924736023},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4634897708892822},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.4530212879180908},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44670307636260986},{"id":"https://openalex.org/C146002875","wikidata":"https://www.wikidata.org/wiki/Q1074289","display_name":"Frequency multiplier","level":3,"score":0.41728657484054565},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.315234512090683},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.2762256860733032},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22817984223365784},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08888527750968933},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2012/546212","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/546212","pdf_url":"https://downloads.hindawi.com/archive/2012/546212.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2012/546212","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2012/546212","pdf_url":"https://downloads.hindawi.com/archive/2012/546212.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320323380","display_name":"Universiti Teknologi Petronas","ror":"https://ror.org/048g2sh07"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2123931172.pdf","grobid_xml":"https://content.openalex.org/works/W2123931172.grobid-xml"},"referenced_works_count":14,"referenced_works":["https://openalex.org/W60344427","https://openalex.org/W1544275318","https://openalex.org/W1580654973","https://openalex.org/W1595854705","https://openalex.org/W1629104240","https://openalex.org/W2013950814","https://openalex.org/W2067333289","https://openalex.org/W2100869429","https://openalex.org/W2131325068","https://openalex.org/W2131484509","https://openalex.org/W2137120286","https://openalex.org/W2141485980","https://openalex.org/W2145339789","https://openalex.org/W2158028499"],"related_works":["https://openalex.org/W3145870900","https://openalex.org/W2350523680","https://openalex.org/W2379961307","https://openalex.org/W2353586717","https://openalex.org/W2382465025","https://openalex.org/W2377156450","https://openalex.org/W2376421545","https://openalex.org/W2374761771","https://openalex.org/W2371350995","https://openalex.org/W2354027044"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,7,67,137,150],"new":[4],"architecture":[5,14,85],"for":[6,48,70,94],"synchronized":[8],"frequency":[9,151],"multiplier":[10],"circuit.":[11,59],"The":[12,83,100,158],"proposed":[13,84],"is":[15,38,86,142],"an":[16,57,120],"all\u2010digital":[17],"dual\u2010loop":[18],"delay\u2010":[19],"and":[20,43,92,117,140],"frequency\u2010locked":[21],"loops":[22],"circuit,":[23],"which":[24],"has":[25,136],"several":[26],"advantages,":[27],"namely,":[28],"it":[29,61,141],"does":[30],"not":[31],"have":[32],"the":[33,89,95,104,111,115,125,132,144,166],"jitter":[34],"accumulation":[35],"issue":[36],"that":[37],"normally":[39],"encountered":[40],"in":[41,65,80,124,143],"PLL":[42],"can":[44,62],"be":[45,63],"adapted":[46],"easily":[47],"different":[49],"FPGA":[50],"families":[51],"as":[52,54,56,75,77,108,110],"well":[53,76,109],"implemented":[55],"integrated":[58],"Moreover,":[60],"used":[64],"supplying":[66],"clock":[68,134],"reference":[69,122],"distributed":[71],"digital":[72],"processing":[73],"systems":[74],"intra/interchip":[78],"communication":[79],"system\u2010on\u2010chip":[81],"(SoC).":[82],"designed":[87],"using":[88,165],"Verilog":[90],"language":[91],"synthesized":[93,159],"Altera":[96,168],"DE2\u201070":[97],"development":[98],"board.":[99,169],"experimental":[101],"results":[102],"validate":[103],"expected":[105],"phase":[106],"tracking":[107],"synthesizing":[112],"properties.":[113],"For":[114],"measurement":[116],"validation":[118],"purpose,":[119],"input":[121],"signal":[123,135],"range":[126,145],"of":[127,146,155],"1.94\u20132.62":[128],"MHz":[129,148],"was":[130],"injected;":[131],"generated":[133],"higher":[138],"frequency,":[139],"124.2\u2013167.9":[147],"with":[149],"step":[152],"(i.e.,":[153],"resolution)":[154],"0.168":[156],"MHz.":[157],"design":[160],"requires":[161],"330":[162],"logic":[163],"elements":[164],"above":[167]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-15T07:11:24.734988","created_date":"2025-10-10T00:00:00"}