{"id":"https://openalex.org/W2056300369","doi":"https://doi.org/10.1155/2011/896241","title":"Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms","display_name":"Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms","publication_year":2011,"publication_date":"2011-10-12","ids":{"openalex":"https://openalex.org/W2056300369","doi":"https://doi.org/10.1155/2011/896241","mag":"2056300369"},"language":"en","primary_location":{"id":"doi:10.1155/2011/896241","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2011/896241","pdf_url":"https://downloads.hindawi.com/archive/2011/896241.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2011/896241.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003786573","display_name":"I.Hameem Shanavas","orcid":"https://orcid.org/0000-0001-8542-9831"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"I. Hameem Shanavas","raw_affiliation_strings":["Department of Electronics and Communication, M. V. J. College of Engineering, Bangalore 560067, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, M. V. J. College of Engineering, Bangalore 560067, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000882575","display_name":"R. K. Gnanamurthy","orcid":"https://orcid.org/0009-0001-3289-530X"},"institutions":[{"id":"https://openalex.org/I4210115326","display_name":"Swami Vivekanand College of Pharmacy","ror":"https://ror.org/029n4n358","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210115326"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ramaswamy Kannan Gnanamurthy","raw_affiliation_strings":["Vivekanandha College of Engineering for Women, Trichengode 637205, Tamilnadu, India"],"affiliations":[{"raw_affiliation_string":"Vivekanandha College of Engineering for Women, Trichengode 637205, Tamilnadu, India","institution_ids":["https://openalex.org/I4210115326"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5003786573"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3248,"has_fulltext":true,"cited_by_count":13,"citation_normalized_percentile":{"value":0.8240705,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"2011","issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.989300012588501,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9324015378952026},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.758247971534729},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.6784902811050415},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6146718859672546},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5017588138580322},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.46468496322631836},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.46310871839523315},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45046916604042053},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40439605712890625},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2921868860721588},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.08821538090705872}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9324015378952026},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.758247971534729},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.6784902811050415},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6146718859672546},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5017588138580322},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.46468496322631836},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.46310871839523315},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45046916604042053},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40439605712890625},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2921868860721588},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.08821538090705872},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2011/896241","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2011/896241","pdf_url":"https://downloads.hindawi.com/archive/2011/896241.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2011/896241","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2011/896241","pdf_url":"https://downloads.hindawi.com/archive/2011/896241.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.49000000953674316,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2056300369.pdf","grobid_xml":"https://content.openalex.org/works/W2056300369.grobid-xml"},"referenced_works_count":23,"referenced_works":["https://openalex.org/W108855261","https://openalex.org/W1524539887","https://openalex.org/W1530822797","https://openalex.org/W1841477732","https://openalex.org/W1904871254","https://openalex.org/W1987786682","https://openalex.org/W2011039300","https://openalex.org/W2024060531","https://openalex.org/W2030605379","https://openalex.org/W2056760934","https://openalex.org/W2088788514","https://openalex.org/W2095117703","https://openalex.org/W2095837253","https://openalex.org/W2144124730","https://openalex.org/W2148992607","https://openalex.org/W2154061444","https://openalex.org/W2158458634","https://openalex.org/W2161455936","https://openalex.org/W2170186790","https://openalex.org/W2241855467","https://openalex.org/W2324696707","https://openalex.org/W2532904897","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2133901311","https://openalex.org/W4311031373","https://openalex.org/W2136768364","https://openalex.org/W4256007160","https://openalex.org/W2087871358","https://openalex.org/W2094042791","https://openalex.org/W4205135025","https://openalex.org/W4386643835","https://openalex.org/W2120361800","https://openalex.org/W2182445672"],"abstract_inverted_index":{"Minimizing":[0],"the":[1,43,57,69,81,123,184],"wirelength":[2,20,125],"plays":[3],"an":[4,27,106],"important":[5],"role":[6],"in":[7,72,76,85,129,135],"physical":[8,32],"design":[9,33,156],"automation":[10],"of":[11,19,45,59,141,146],"very":[12],"large-scale":[13],"integration":[14],"(VLSI)":[15],"chips.":[16],"The":[17,83,151],"objective":[18],"minimization":[21],"can":[22,178],"be":[23],"achieved":[24],"by":[25,126,132],"finding":[26],"optimal":[28,181],"solution":[29],"for":[30,144,167,183],"VLSI":[31,40,54,147,172],"components":[34],"like":[35,94,158,164],"partitioning":[36,73,86,130,148,173],"and":[37,74,87,99,131,149,161,174],"floorplanning.":[38,136,150],"In":[39,53],"circuit":[41,55],"partitioning,":[42],"problem":[44,58],"obtaining":[46],"a":[47,65,154],"minimum":[48,70,124],"delay":[49,71,128],"has":[50],"prime":[51],"importance.":[52],"floorplanning,":[56],"minimizing":[60],"silicon":[61],"area":[62,75,134],"is":[63,105],"also":[64],"hot":[66],"issue.":[67],"Reducing":[68],"floorplanning":[77,88,175],"helps":[78],"to":[79,121,170],"minimize":[80],"wirelength.":[82],"enhancements":[84],"have":[89],"influence":[90],"on":[91],"other":[92],"criteria":[93],"power,":[95],"cost,":[96],"clock":[97],"speed,":[98],"so":[100],"forth.":[101],"Memetic":[102],"Algorithm":[103,108],"(MA)":[104],"Evolutionary":[107],"that":[109],"includes":[110],"one":[111],"or":[112],"more":[113],"local":[114,142,168],"search":[115,143,169],"phases":[116],"within":[117],"its":[118],"evolutionary":[119],"cycle":[120],"obtain":[122],"reducing":[127,133],"MA":[137,177],"applies":[138],"some":[139],"sort":[140],"optimization":[145],"algorithm":[152,160],"combines":[153],"hierarchical":[155],"technique":[157,163],"genetic":[159],"constructive":[162],"Simulated":[165],"Annealing":[166],"solve":[171],"problem.":[176],"quickly":[179],"produce":[180],"solutions":[182],"popular":[185],"benchmark.":[186]},"counts_by_year":[{"year":2021,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}