{"id":"https://openalex.org/W2026546991","doi":"https://doi.org/10.1155/2010/697625","title":"Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs","display_name":"Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W2026546991","doi":"https://doi.org/10.1155/2010/697625","mag":"2026546991"},"language":"en","primary_location":{"id":"doi:10.1155/2010/697625","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2010/697625","pdf_url":"https://downloads.hindawi.com/journals/ijrc/2010/697625.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://downloads.hindawi.com/journals/ijrc/2010/697625.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101884988","display_name":"Shahnam Mirzaei","orcid":"https://orcid.org/0000-0003-0238-8697"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shahnam Mirzaei","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA"],"raw_orcid":"https://orcid.org/0000-0003-0238-8697","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000231774","display_name":"Ryan Kastner","orcid":"https://orcid.org/0000-0001-9062-5570"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ryan Kastner","raw_affiliation_strings":["Cadence Design Systems, University of California, San Diego, CA 95134, USA"],"raw_orcid":"https://orcid.org/0000-0001-9062-5570","affiliations":[{"raw_affiliation_string":"Cadence Design Systems, University of California, San Diego, CA 95134, USA","institution_ids":["https://openalex.org/I36258959","https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008405920","display_name":"Anup Hosangadi","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anup Hosangadi","raw_affiliation_strings":["Department of Computer Science and Engineering, Cadence, La Jolla, CA 92093, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Cadence, La Jolla, CA 92093, USA","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":925,"currency":"USD","value_usd":925},"apc_paid":{"value":925,"currency":"USD","value_usd":925},"fwci":3.4745,"has_fulltext":true,"cited_by_count":22,"citation_normalized_percentile":{"value":0.92063854,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"2010","issue":null,"first_page":"1","last_page":"17"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8227673768997192},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7792558670043945},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7774375081062317},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.7652010321617126},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6371229887008667},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5667696595191956},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4856818616390228},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.4802682399749756},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.420820415019989},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40929943323135376},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3975133001804352},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33419036865234375},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.16789066791534424},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16122567653656006},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0775977373123169}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8227673768997192},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7792558670043945},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7774375081062317},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.7652010321617126},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6371229887008667},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5667696595191956},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4856818616390228},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.4802682399749756},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.420820415019989},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40929943323135376},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3975133001804352},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33419036865234375},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.16789066791534424},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16122567653656006},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0775977373123169},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/2010/697625","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2010/697625","pdf_url":"https://downloads.hindawi.com/journals/ijrc/2010/697625.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:2887d08ebd124d47891b07fbdaa68acf","is_oa":true,"landing_page_url":"https://doaj.org/article/2887d08ebd124d47891b07fbdaa68acf","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"International Journal of Reconfigurable Computing, Vol 2010 (2010)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2010/697625","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2010/697625","pdf_url":"https://downloads.hindawi.com/journals/ijrc/2010/697625.pdf","source":{"id":"https://openalex.org/S194867674","display_name":"International Journal of Reconfigurable Computing","issn_l":"1687-7195","issn":["1687-7195","1687-7209"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Reconfigurable Computing","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8500000238418579}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2026546991.pdf","grobid_xml":"https://content.openalex.org/works/W2026546991.grobid-xml"},"referenced_works_count":39,"referenced_works":["https://openalex.org/W201024842","https://openalex.org/W1525754243","https://openalex.org/W1538008395","https://openalex.org/W1553214226","https://openalex.org/W1590193206","https://openalex.org/W1590348499","https://openalex.org/W1600572839","https://openalex.org/W1980816824","https://openalex.org/W1981252059","https://openalex.org/W1984435650","https://openalex.org/W1984615619","https://openalex.org/W1991900639","https://openalex.org/W1995422957","https://openalex.org/W2001184806","https://openalex.org/W2001254103","https://openalex.org/W2020842839","https://openalex.org/W2053257054","https://openalex.org/W2103244632","https://openalex.org/W2106351882","https://openalex.org/W2108956554","https://openalex.org/W2109249643","https://openalex.org/W2117373759","https://openalex.org/W2120173944","https://openalex.org/W2121208961","https://openalex.org/W2123008137","https://openalex.org/W2130227050","https://openalex.org/W2133346263","https://openalex.org/W2133932834","https://openalex.org/W2139637699","https://openalex.org/W2141136781","https://openalex.org/W2141287958","https://openalex.org/W2142508560","https://openalex.org/W2144832424","https://openalex.org/W2154656381","https://openalex.org/W2155747143","https://openalex.org/W2167523715","https://openalex.org/W2218880787","https://openalex.org/W2268169265","https://openalex.org/W2286267069"],"related_works":["https://openalex.org/W3082309838","https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W2131696304","https://openalex.org/W4387951306","https://openalex.org/W2374017528","https://openalex.org/W2142508560","https://openalex.org/W4239932082","https://openalex.org/W4285503609","https://openalex.org/W2126248441"],"abstract_inverted_index":{"We":[0,115],"present":[1],"a":[2,22,32,52,186],"method":[3],"for":[4,139],"implementing":[5],"high":[6],"speed":[7],"finite":[8],"impulse":[9],"response":[10],"(FIR)":[11],"filters":[12,173],"on":[13,111],"field":[14],"programmable":[15],"gate":[16],"arrays":[17],"(FPGAs).":[18],"Our":[19,161],"algorithm":[20,44,58],"is":[21,109,149,185],"multiplierless":[23],"technique":[24],"where":[25,96],"fixed":[26],"coefficient":[27],"multipliers":[28],"are":[29,91],"replaced":[30],"with":[31,102],"series":[33],"of":[34,42,62,124,134,158,193],"add":[35],"and":[36,48,84,126,201],"shift":[37],"operations.":[38],"The":[39,67,87],"first":[40],"phase":[41,69],"our":[43],"uses":[45],"registered":[46],"adders":[47,63],"hardwired":[49],"shifts.":[50],"Here,":[51],"modified":[53],"common":[54],"subexpression":[55],"elimination":[56],"(CSE)":[57],"reduces":[59],"the":[60,81,99,122,132,153,159,169],"number":[61,123,133,192],"while":[64],"maintaining":[65],"performance.":[66],"second":[68],"optimizes":[70],"routing":[71,194],"delay":[72],"using":[73,179],"prelayout":[74],"wire":[75],"length":[76],"estimation":[77],"techniques":[78],"to":[79,118,128,144,165,189,203],"improve":[80],"final":[82],"placed":[83],"routed":[85],"design.":[86],"optimization":[88],"target":[89],"platforms":[90],"Xilinx":[92,106,176],"Virtex":[93],"FPGA":[94],"devices":[95],"we":[97],"compare":[98],"implementation":[100],"results":[101,197],"those":[103],"produced":[104],"by":[105,175],"Coregen,":[107],"which":[108],"based":[110],"distributed":[112],"arithmetic":[113],"(DA).":[114],"observed":[116],"up":[117,127,136,164,188,202],"50%":[119,150],"reduction":[120,130,151,205],"in":[121,131,152,191,198,206],"slices":[125],"75%":[129],"look":[135],"tables":[137],"(LUTs)":[138],"fully":[140],"parallel":[141],"implementations":[142],"compared":[143],"DA":[145],"method.":[146],"Also,":[147],"there":[148,184],"total":[154],"dynamic":[155],"power":[156],"consumption":[157],"filters.":[160],"designs":[162],"perform":[163],"27%":[166],"faster":[167],"than":[168],"multiply":[170],"accumulate":[171],"(MAC)":[172],"implemented":[174],"Coregen":[177],"tool":[178],"DSP":[180],"blocks.":[181],"For":[182],"placement,":[183],"saving":[187],"20%":[190],"channels.":[195],"This":[196],"lower":[199],"congestion":[200],"8%":[204],"average":[207],"wirelength.":[208]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-23T08:03:31.855105","created_date":"2025-10-10T00:00:00"}