{"id":"https://openalex.org/W2008881235","doi":"https://doi.org/10.1155/2010/639747","title":"An Approach for Implementing State Machines with Online Testability","display_name":"An Approach for Implementing State Machines with Online Testability","publication_year":2010,"publication_date":"2010-04-28","ids":{"openalex":"https://openalex.org/W2008881235","doi":"https://doi.org/10.1155/2010/639747","mag":"2008881235"},"language":"en","primary_location":{"id":"doi:10.1155/2010/639747","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2010/639747","pdf_url":"https://downloads.hindawi.com/archive/2010/639747.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2010/639747.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111510680","display_name":"P.K. Lala","orcid":null},"institutions":[{"id":"https://openalex.org/I51380931","display_name":"Texas A&M University \u2013 Texarkana","ror":"https://ror.org/01x3z9745","country_code":"US","type":"education","lineage":["https://openalex.org/I51380931"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"P. K. Lala","raw_affiliation_strings":["Department of Electrical Engineering, Texas A&M University, Texarkana, TX 75505, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Texas A&M University, Texarkana, TX 75505, USA","institution_ids":["https://openalex.org/I51380931"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066852044","display_name":"A. Mathews","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Mathews","raw_affiliation_strings":["Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR 72701, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR 72701, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039873885","display_name":"J.P. Parkerson","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. P. Parkerson","raw_affiliation_strings":["Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR 72701, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR 72701, USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111510680"],"corresponding_institution_ids":["https://openalex.org/I51380931"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.08736623,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"2010","issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12423","display_name":"Software Reliability and Analysis Research","score":0.9908000230789185,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7733118534088135},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7170631289482117},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.6250597834587097},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.6084330081939697},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5856758952140808},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5401638150215149},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5378988981246948},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5216689109802246},{"id":"https://openalex.org/keywords/transient","display_name":"Transient (computer programming)","score":0.5150954127311707},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.4517388641834259},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4435771107673645},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37882933020591736},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3605473041534424},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3411772549152374},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.304538369178772},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.30249232053756714},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2581460773944855},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1933617889881134},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.15464672446250916},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1313977837562561},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10340535640716553}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7733118534088135},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7170631289482117},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.6250597834587097},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.6084330081939697},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5856758952140808},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5401638150215149},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5378988981246948},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5216689109802246},{"id":"https://openalex.org/C2780799671","wikidata":"https://www.wikidata.org/wiki/Q17087362","display_name":"Transient (computer programming)","level":2,"score":0.5150954127311707},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.4517388641834259},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4435771107673645},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37882933020591736},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3605473041534424},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3411772549152374},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.304538369178772},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.30249232053756714},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2581460773944855},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1933617889881134},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.15464672446250916},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1313977837562561},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10340535640716553},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2010/639747","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2010/639747","pdf_url":"https://downloads.hindawi.com/archive/2010/639747.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2010/639747","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2010/639747","pdf_url":"https://downloads.hindawi.com/archive/2010/639747.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2884306010","display_name":null,"funder_award_id":"0925080","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2008881235.pdf","grobid_xml":"https://content.openalex.org/works/W2008881235.grobid-xml"},"referenced_works_count":16,"referenced_works":["https://openalex.org/W562038582","https://openalex.org/W1548975601","https://openalex.org/W1725240622","https://openalex.org/W1883730619","https://openalex.org/W1970717833","https://openalex.org/W1973876091","https://openalex.org/W1978921131","https://openalex.org/W2052461569","https://openalex.org/W2100219166","https://openalex.org/W2104122494","https://openalex.org/W2121942050","https://openalex.org/W2128015543","https://openalex.org/W2162465831","https://openalex.org/W2162532189","https://openalex.org/W2166267546","https://openalex.org/W2535232012"],"related_works":["https://openalex.org/W2141941412","https://openalex.org/W2069145203","https://openalex.org/W1702800398","https://openalex.org/W2085176210","https://openalex.org/W2106889348","https://openalex.org/W2083793411","https://openalex.org/W2135500595","https://openalex.org/W2543766998","https://openalex.org/W573124066","https://openalex.org/W1969171031"],"abstract_inverted_index":{"During":[0],"the":[1,14,63],"last":[2],"two":[3],"decades,":[4],"significant":[5],"amount":[6],"of":[7,16,50,65,74,83],"research":[8],"has":[9,91],"been":[10,93],"performed":[11],"to":[12,70],"simplify":[13],"detection":[15,49,90],"transient":[17],"or":[18],"soft":[19,51],"errors":[20,52],"in":[21,53],"VLSI-based":[22],"digital":[23],"systems.":[24],"This":[25],"paper":[26],"proposes":[27],"an":[28],"approach":[29,46],"for":[30,38,87],"implementing":[31],"state":[32,39,76],"machines":[33,42],"that":[34],"uses":[35],"2-hot":[36,59],"code":[37,60],"encoding.":[40],"State":[41],"designed":[43],"using":[44],"this":[45],"allow":[47],"online":[48,88],"registers":[54],"and":[55,68,77],"output":[56,78,85],"logic.":[57,79],"The":[58],"considerably":[61],"reduces":[62],"number":[64],"required":[66],"flip-flops":[67],"leads":[69],"relatively":[71],"straightforward":[72],"implementation":[73],"next":[75],"A":[80],"new":[81],"way":[82],"designing":[84],"logic":[86],"fault":[89],"also":[92],"presented.":[94]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}