{"id":"https://openalex.org/W1994884893","doi":"https://doi.org/10.1155/2009/156751","title":"Floorplan-Driven Multivoltage High-Level Synthesis","display_name":"Floorplan-Driven Multivoltage High-Level Synthesis","publication_year":2009,"publication_date":"2009-09-06","ids":{"openalex":"https://openalex.org/W1994884893","doi":"https://doi.org/10.1155/2009/156751","mag":"1994884893"},"language":"en","primary_location":{"id":"doi:10.1155/2009/156751","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2009/156751","pdf_url":"https://downloads.hindawi.com/archive/2009/156751.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2009/156751.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029379975","display_name":"Xianwu Xing","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Xianwu Xing","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018516888","display_name":"Ching Chuen Jong","orcid":"https://orcid.org/0000-0003-1178-9062"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Ching Chuen Jong","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5018516888"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":0.2638,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54879132,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2009","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9263730049133301},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.8508526086807251},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.797103762626648},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7083337306976318},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6043129563331604},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5646173357963562},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5242907404899597},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4726528227329254},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33378416299819946},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2886159121990204},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20524686574935913},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.15242189168930054},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.12257367372512817},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07182005047798157}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9263730049133301},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.8508526086807251},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.797103762626648},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7083337306976318},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6043129563331604},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5646173357963562},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5242907404899597},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4726528227329254},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33378416299819946},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2886159121990204},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20524686574935913},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.15242189168930054},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.12257367372512817},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07182005047798157}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2009/156751","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2009/156751","pdf_url":"https://downloads.hindawi.com/archive/2009/156751.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2009/156751","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2009/156751","pdf_url":"https://downloads.hindawi.com/archive/2009/156751.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8700000047683716,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1994884893.pdf","grobid_xml":"https://content.openalex.org/works/W1994884893.grobid-xml"},"referenced_works_count":22,"referenced_works":["https://openalex.org/W1483017465","https://openalex.org/W1981191385","https://openalex.org/W1999640823","https://openalex.org/W2008689571","https://openalex.org/W2011579672","https://openalex.org/W2032444288","https://openalex.org/W2051230585","https://openalex.org/W2052031047","https://openalex.org/W2074601596","https://openalex.org/W2094042791","https://openalex.org/W2097053919","https://openalex.org/W2100045226","https://openalex.org/W2108904252","https://openalex.org/W2115118594","https://openalex.org/W2119899316","https://openalex.org/W2123611365","https://openalex.org/W2125527825","https://openalex.org/W2138444824","https://openalex.org/W2151997136","https://openalex.org/W2153986094","https://openalex.org/W2160020444","https://openalex.org/W2169278276"],"related_works":["https://openalex.org/W2120659218","https://openalex.org/W2534955606","https://openalex.org/W2133901311","https://openalex.org/W2136768364","https://openalex.org/W2087871358","https://openalex.org/W4386643835","https://openalex.org/W2120361800","https://openalex.org/W2182445672","https://openalex.org/W1903431847","https://openalex.org/W2166021916"],"abstract_inverted_index":{"As":[0],"the":[1,41,84,90,95,98],"semiconductor":[2],"technology":[3],"advances,":[4],"interconnect":[5],"plays":[6],"a":[7,22,61],"more":[8,10,104],"and":[9,33,46,53,89,97],"important":[11],"role":[12],"in":[13,16,24,27],"power":[14],"consumption":[15],"VLSI":[17,74],"systems.":[18],"This":[19],"also":[20],"imposes":[21],"challenge":[23],"high-level":[25,37,44,54,71],"synthesis,":[26],"which":[28],"physical":[29,47,51],"information":[30],"is":[31,56,65,87],"limited":[32],"conventionally":[34],"considered":[35],"after":[36],"synthesis.":[38],"To":[39],"close":[40],"gap":[42],"between":[43],"synthesis":[45,52,55,72],"implementation,":[48],"integration":[49],"of":[50,73],"essential.":[57],"In":[58],"this":[59],"paper,":[60],"technique":[62,86],"named":[63],"FloM":[64],"proposed":[66,85],"for":[67],"integrating":[68],"floorplanning":[69],"into":[70],"system":[75],"with":[76],"multivoltage":[77],"datapath.":[78],"Experimental":[79],"results":[80],"obtained":[81],"show":[82],"that":[83],"effective":[88],"energy":[91],"consumed":[92],"by":[93,103],"both":[94],"datapath":[96],"wires":[99],"can":[100],"be":[101],"reduced":[102],"than":[105],"40%.":[106]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
