{"id":"https://openalex.org/W2105643801","doi":"https://doi.org/10.1155/2008/218565","title":"Delay Efficient 32\u2010Bit Carry\u2010Skip Adder","display_name":"Delay Efficient 32\u2010Bit Carry\u2010Skip Adder","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2105643801","doi":"https://doi.org/10.1155/2008/218565","mag":"2105643801"},"language":"en","primary_location":{"id":"doi:10.1155/2008/218565","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2008/218565","pdf_url":"https://downloads.hindawi.com/archive/2008/218565.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2008/218565.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020439055","display_name":"Yu Shen Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yu Shen Lin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, State University of New York, New Paltz, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State University of New York, New Paltz, NY","institution_ids":["https://openalex.org/I1327163397"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016682513","display_name":"D. Radhakrishnan","orcid":null},"institutions":[{"id":"https://openalex.org/I1327163397","display_name":"State University of New York","ror":"https://ror.org/01q1z8k08","country_code":"US","type":"education","lineage":["https://openalex.org/I1327163397"]},{"id":"https://openalex.org/I157455823","display_name":"SUNY New Paltz","ror":"https://ror.org/03j3dv688","country_code":"US","type":"education","lineage":["https://openalex.org/I157455823"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Damu Radhakrishnan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, State University of New York, 1 Hawk Dr, New Paltz, NY 12561-2443, USA","Department of Electrical and Computer Engineering, State University of New York, New Paltz, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State University of New York, 1 Hawk Dr, New Paltz, NY 12561-2443, USA","institution_ids":["https://openalex.org/I157455823"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State University of New York, New Paltz, NY","institution_ids":["https://openalex.org/I1327163397"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6718,"has_fulltext":true,"cited_by_count":11,"citation_normalized_percentile":{"value":0.73421166,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"2008","issue":"1","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9732869267463684},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.8690831661224365},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.7020756006240845},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.6834805011749268},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5928519368171692},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5427979826927185},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.525599479675293},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.501370906829834},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4202503263950348},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.4157980978488922},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40963611006736755},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3173147141933441},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.26205968856811523},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1178959310054779},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06894662976264954}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9732869267463684},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.8690831661224365},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.7020756006240845},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.6834805011749268},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5928519368171692},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5427979826927185},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.525599479675293},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.501370906829834},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4202503263950348},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.4157980978488922},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40963611006736755},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3173147141933441},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.26205968856811523},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1178959310054779},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06894662976264954},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2008/218565","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2008/218565","pdf_url":"https://downloads.hindawi.com/archive/2008/218565.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2008/218565","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2008/218565","pdf_url":"https://downloads.hindawi.com/archive/2008/218565.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5699999928474426,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2105643801.pdf","grobid_xml":"https://content.openalex.org/works/W2105643801.grobid-xml"},"referenced_works_count":13,"referenced_works":["https://openalex.org/W1584008964","https://openalex.org/W1587217691","https://openalex.org/W1980597174","https://openalex.org/W1981689635","https://openalex.org/W1993589577","https://openalex.org/W2031375259","https://openalex.org/W2119964324","https://openalex.org/W2127729806","https://openalex.org/W2147686711","https://openalex.org/W2168543008","https://openalex.org/W2536230652","https://openalex.org/W4210830821","https://openalex.org/W4247911538"],"related_works":["https://openalex.org/W2064215635","https://openalex.org/W986131379","https://openalex.org/W1976039195","https://openalex.org/W2605666407","https://openalex.org/W1584617340","https://openalex.org/W2950842282","https://openalex.org/W2157955791","https://openalex.org/W2003324248","https://openalex.org/W2127980940","https://openalex.org/W2532181444"],"abstract_inverted_index":{"The":[0,42,60,73,90,103,113],"design":[1],"of":[2,35,38],"a":[3],"32\u2010bit":[4],"carry\u2010skip":[5,88,129],"adder":[6,91,109,120],"to":[7,30],"achieve":[8],"minimum":[9],"delay":[10,105],"is":[11,28,92,110,121],"presented":[12],"in":[13,51,82,94],"this":[14],"paper.":[15],"A":[16],"fast":[17],"carry":[18,40,55,80],"look\u2010ahead":[19],"logic":[20],"using":[21],"group":[22,25,43,46],"generate":[23,44],"and":[24,45,79],"propagate":[26,47],"functions":[27,48],"used":[29],"speed":[31],"up":[32],"the":[33,54,68,77,107,118,126],"performance":[34],"multiple":[36],"stages":[37],"ripple":[39],"adders.":[41,89],"are":[49,64],"generated":[50],"parallel":[52],"with":[53],"generation":[56],"for":[57,106],"each":[58],"block.":[59],"optimum":[61],"block":[62],"sizes":[63],"decided":[65],"by":[66],"considering":[67],"critical":[69,104],"path":[70],"into":[71],"account.":[72],"new":[74],"architecture":[75],"delivers":[76],"sum":[78],"outputs":[81],"lesser":[83],"unit":[84],"delays":[85],"than":[86,125],"existing":[87],"implemented":[93],"0.25":[95],"\u03bc":[96],"m":[97],"CMOS":[98],"technology":[99],"at":[100],"3.3":[101],"V.":[102],"proposed":[108,119],"3.4":[111],"nanoseconds.":[112],"simulation":[114],"results":[115],"show":[116],"that":[117],"18":[122],"%":[123],"faster":[124],"current":[127],"fastest":[128],"adder.":[130]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}