{"id":"https://openalex.org/W2027354824","doi":"https://doi.org/10.1155/2007/71684","title":"Advanced Readout System IC Current Mode Semi-Gaussian Shapers Using CCIIs and OTAs","display_name":"Advanced Readout System IC Current Mode Semi-Gaussian Shapers Using CCIIs and OTAs","publication_year":2007,"publication_date":"2007-04-12","ids":{"openalex":"https://openalex.org/W2027354824","doi":"https://doi.org/10.1155/2007/71684","mag":"2027354824"},"language":"en","primary_location":{"id":"doi:10.1155/2007/71684","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2007/71684","pdf_url":"https://downloads.hindawi.com/archive/2007/071684.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2007/071684.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087507244","display_name":"T. Noulis","orcid":"https://orcid.org/0000-0002-1867-7488"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Thomas Noulis","raw_affiliation_strings":["Section of Electronics and Computers, Electronics Laboratory, Physics Department, Aristotle University of Thessaloniki, Aristotle University Campus, Greece"],"raw_orcid":"https://orcid.org/0000-0002-1867-7488","affiliations":[{"raw_affiliation_string":"Section of Electronics and Computers, Electronics Laboratory, Physics Department, Aristotle University of Thessaloniki, Aristotle University Campus, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052364340","display_name":"C. Deradonis","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Constantinos Deradonis","raw_affiliation_strings":["Section of Electronics and Computers, Electronics Laboratory, Physics Department, Aristotle University of Thessaloniki, Aristotle University Campus, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Section of Electronics and Computers, Electronics Laboratory, Physics Department, Aristotle University of Thessaloniki, Aristotle University Campus, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025525864","display_name":"S. Siskos","orcid":"https://orcid.org/0000-0002-9506-9435"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Stylianos Siskos","raw_affiliation_strings":["Section of Electronics and Computers, Electronics Laboratory, Physics Department, Aristotle University of Thessaloniki, Aristotle University Campus, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Section of Electronics and Computers, Electronics Laboratory, Physics Department, Aristotle University of Thessaloniki, Aristotle University Campus, Greece","institution_ids":["https://openalex.org/I21370196"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0785,"has_fulltext":true,"cited_by_count":15,"citation_normalized_percentile":{"value":0.77969271,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"2007","issue":null,"first_page":"1","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/total-harmonic-distortion","display_name":"Total harmonic distortion","score":0.7050563097000122},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6418576240539551},{"id":"https://openalex.org/keywords/transconductance","display_name":"Transconductance","score":0.633355975151062},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5488130450248718},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.47578346729278564},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.43400654196739197},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4200389087200165},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3407621383666992},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3090614080429077},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16430380940437317},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1363469660282135}],"concepts":[{"id":"https://openalex.org/C42156128","wikidata":"https://www.wikidata.org/wiki/Q162641","display_name":"Total harmonic distortion","level":3,"score":0.7050563097000122},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6418576240539551},{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.633355975151062},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5488130450248718},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.47578346729278564},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.43400654196739197},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4200389087200165},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3407621383666992},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3090614080429077},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16430380940437317},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1363469660282135}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2007/71684","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2007/71684","pdf_url":"https://downloads.hindawi.com/archive/2007/071684.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2007/71684","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2007/71684","pdf_url":"https://downloads.hindawi.com/archive/2007/071684.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2027354824.pdf","grobid_xml":"https://content.openalex.org/works/W2027354824.grobid-xml"},"referenced_works_count":24,"referenced_works":["https://openalex.org/W571998034","https://openalex.org/W1484306781","https://openalex.org/W1552717389","https://openalex.org/W1902725580","https://openalex.org/W1986330971","https://openalex.org/W2007372746","https://openalex.org/W2022255835","https://openalex.org/W2023418096","https://openalex.org/W2027991779","https://openalex.org/W2029378192","https://openalex.org/W2030208715","https://openalex.org/W2074083817","https://openalex.org/W2095351048","https://openalex.org/W2100187351","https://openalex.org/W2113584709","https://openalex.org/W2129797382","https://openalex.org/W2134107057","https://openalex.org/W2134238920","https://openalex.org/W2139619909","https://openalex.org/W2141126509","https://openalex.org/W2142131444","https://openalex.org/W2144853012","https://openalex.org/W2166270924","https://openalex.org/W2168912615"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W2096437374","https://openalex.org/W1943174035","https://openalex.org/W2131637933","https://openalex.org/W4309675538","https://openalex.org/W2123889547","https://openalex.org/W4294672479","https://openalex.org/W2281911854","https://openalex.org/W2774183083","https://openalex.org/W3216209837"],"abstract_inverted_index":{"Novel":[0],"CMOS":[1],"current":[2,20],"mode":[3],"shapers":[4],"for":[5],"front-end":[6],"electronics":[7],"are":[8,26,37,49,83],"proposed.":[9],"In":[10],"particular,":[11],"six":[12],"semi-Gaussian":[13],"shaper":[14,35,89],"implementations":[15],"based":[16],"on":[17],"second":[18],"generation":[19],"conveyors":[21],"and":[22,63],"operational":[23],"transconductance":[24],"amplifiers":[25],"designed":[27],"using":[28,98],"advanced":[29],"filter":[30],"design":[31],"techniques.":[32],"Although":[33],"all":[34],"architectures":[36],"fully":[38],"integrated,":[39],"they":[40],"satisfy":[41],"a":[42,101],"relatively":[43],"large":[44],"peaking":[45],"time.":[46],"The":[47],"topologies":[48],"analytically":[50],"compared":[51],"in":[52,67,76,85,100],"terms":[53],"of":[54],"noise":[55],"performance,":[56],"power":[57],"consumption,":[58],"total":[59],"harmonic":[60],"distortion":[61],"(THD),":[62],"dynamic":[64],"range":[65],"(DR)":[66],"order":[68],"to":[69,87],"examine":[70],"which":[71],"is":[72,93],"the":[73,88],"most":[74],"preferable":[75],"readout":[77],"applications.":[78],"Design":[79],"technique":[80],"selection":[81],"criteria":[82],"proposed":[84],"relation":[86],"structures":[90],"performance.":[91],"Analysis":[92],"supported":[94],"by":[95,106],"simulations":[96],"results":[97],"SPICE":[99],"0.6":[102],"<mml:math":[103],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"><mml:mi>\u03bc</mml:mi></mml:math>m":[104],"process":[105],"Austria":[107],"Mikro":[108],"Systeme":[109],"(AMS).":[110]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
