{"id":"https://openalex.org/W2072959483","doi":"https://doi.org/10.1155/2007/50285","title":"Area and Power Modeling for Networks-on-Chip with Layout Awareness","display_name":"Area and Power Modeling for Networks-on-Chip with Layout Awareness","publication_year":2007,"publication_date":"2007-04-30","ids":{"openalex":"https://openalex.org/W2072959483","doi":"https://doi.org/10.1155/2007/50285","mag":"2072959483"},"language":"en","primary_location":{"id":"doi:10.1155/2007/50285","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2007/50285","pdf_url":"https://downloads.hindawi.com/archive/2007/050285.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2007/050285.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050421874","display_name":"Paolo Meloni","orcid":"https://orcid.org/0000-0002-8106-4641"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Paolo Meloni","raw_affiliation_strings":["Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046255006","display_name":"Igor Loi","orcid":"https://orcid.org/0000-0003-3852-4662"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]},{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Igor Loi","raw_affiliation_strings":["Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy","Department of Electronics and Information Scince  (DEIS), University of Bologna, Bologna 40136, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy","institution_ids":["https://openalex.org/I172446870"]},{"raw_affiliation_string":"Department of Electronics and Information Scince  (DEIS), University of Bologna, Bologna 40136, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091526399","display_name":"Federico Angiolini","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Federico Angiolini","raw_affiliation_strings":["Department of Electronics and Information Scince  (DEIS), University of Bologna, Bologna 40136, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Scince  (DEIS), University of Bologna, Bologna 40136, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069275031","display_name":"Salvatore Carta","orcid":"https://orcid.org/0000-0001-9481-511X"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Salvatore Carta","raw_affiliation_strings":["Department of  Mathematics and Information Science, University of Cagliari, Cagliari 09123, Italy"],"affiliations":[{"raw_affiliation_string":"Department of  Mathematics and Information Science, University of Cagliari, Cagliari 09123, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002078286","display_name":"Massimo Barbaro","orcid":"https://orcid.org/0000-0001-6136-7664"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Massimo Barbaro","raw_affiliation_strings":["Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007761671","display_name":"Luigi Raffo","orcid":"https://orcid.org/0000-0001-9683-009X"},"institutions":[{"id":"https://openalex.org/I172446870","display_name":"University of Cagliari","ror":"https://ror.org/003109y17","country_code":"IT","type":"education","lineage":["https://openalex.org/I172446870"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luigi Raffo","raw_affiliation_strings":["Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy","institution_ids":["https://openalex.org/I172446870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["Department of Electronics and Information Scince  (DEIS), University of Bologna, Bologna 40136, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Information Scince  (DEIS), University of Bologna, Bologna 40136, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5050421874"],"corresponding_institution_ids":["https://openalex.org/I172446870"],"apc_list":null,"apc_paid":null,"fwci":4.376,"has_fulltext":true,"cited_by_count":31,"citation_normalized_percentile":{"value":0.94520145,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"2007","issue":null,"first_page":"1","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10179","display_name":"Supercapacitor Materials and Fabrication","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10018","display_name":"Advancements in Battery Materials","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6979232430458069},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6738803386688232},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6539133787155151},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6472995281219482},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6268619298934937},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5907505750656128},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.46955186128616333},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.464702308177948},{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.46445250511169434},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43900057673454285},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.43731677532196045},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4332711100578308},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.41921067237854004},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41710546612739563},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4146226942539215},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4024716913700104},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.34093785285949707},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25100189447402954},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17950892448425293},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09724929928779602}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6979232430458069},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6738803386688232},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6539133787155151},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6472995281219482},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6268619298934937},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5907505750656128},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.46955186128616333},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.464702308177948},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.46445250511169434},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43900057673454285},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.43731677532196045},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4332711100578308},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.41921067237854004},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41710546612739563},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4146226942539215},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4024716913700104},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.34093785285949707},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25100189447402954},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17950892448425293},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09724929928779602},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1155/2007/50285","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2007/50285","pdf_url":"https://downloads.hindawi.com/archive/2007/050285.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.133.4497","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.133.4497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www-micrel.deis.unibo.it/~angiolini/vlsid07.pdf","raw_type":"text"},{"id":"pmh:oai:cris.unibo.it:11585/49288","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/49288","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:iris.unica.it:11584/106499","is_oa":false,"landing_page_url":"http://hdl.handle.net/11584/106499","pdf_url":null,"source":{"id":"https://openalex.org/S4377196293","display_name":"UNICA IRIS Institutional Research Information System (University of Cagliari)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172446870","host_organization_name":"University of Cagliari","host_organization_lineage":["https://openalex.org/I172446870"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"doi:10.1155/2007/50285","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2007/50285","pdf_url":"https://downloads.hindawi.com/archive/2007/050285.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2072959483.pdf","grobid_xml":"https://content.openalex.org/works/W2072959483.grobid-xml"},"referenced_works_count":23,"referenced_works":["https://openalex.org/W61386972","https://openalex.org/W1582835330","https://openalex.org/W2011403724","https://openalex.org/W2054302810","https://openalex.org/W2098996548","https://openalex.org/W2102387714","https://openalex.org/W2102727118","https://openalex.org/W2103066735","https://openalex.org/W2108783911","https://openalex.org/W2111700531","https://openalex.org/W2111919017","https://openalex.org/W2118799833","https://openalex.org/W2123184444","https://openalex.org/W2127430446","https://openalex.org/W2128087858","https://openalex.org/W2132727849","https://openalex.org/W2142773463","https://openalex.org/W2144293278","https://openalex.org/W2154628372","https://openalex.org/W2158206751","https://openalex.org/W2160642395","https://openalex.org/W2171940713","https://openalex.org/W2545278413"],"related_works":["https://openalex.org/W2388672758","https://openalex.org/W2135981148","https://openalex.org/W2754086592","https://openalex.org/W2144357574","https://openalex.org/W2065289416","https://openalex.org/W3198758847","https://openalex.org/W4230458348","https://openalex.org/W1966325333","https://openalex.org/W1581055755","https://openalex.org/W2519428907"],"abstract_inverted_index":{"Networks-on-Chip":[0],"(NoCs)":[1],"are":[2,17,57,106,197],"emerging":[3,59],"as":[4,109,114],"scalable":[5],"interconnection":[6],"architectures,":[7],"designed":[8],"to":[9,24,36,126,132,163,225],"support":[10],"the":[11,38,48,70,87,94,213,216],"increasing":[12],"amount":[13,40],"of":[14,41,44,50,89,96,167,173,188,191,215],"cores":[15],"that":[16,77],"integrated":[18],"onto":[19],"a":[20,51,142,161],"silicon":[21],"die.":[22],"Compared":[23],"traditional":[25,117],"interconnects,":[26],"however,":[27,92],"NoCs":[28],"still":[29],"lack":[30],"well":[31,112],"established":[32],"CAD":[33],"deployment":[34],"tools":[35,56],"tackle":[37],"large":[39],"available":[42,110],"degrees":[43],"freedom,":[45],"starting":[46],"from":[47],"choice":[49],"network":[52],"topology.":[53],"\u201cSilicon-aware\u201d":[54],"optimization":[55],"now":[58],"in":[60,186,207],"literature;":[61],"they":[62,220],"select":[63],"an":[64,155],"NoC":[65,156,174,229],"topology":[66],"taking":[67],"into":[68],"account":[69],"tradeoff":[71],"between":[72],"performance":[73],"and":[74,80,102,111,148,170,176,190,203,227],"hardware":[75],"cost,":[76],"is,":[78],"area":[79,168],"power":[81,101,171],"consumption.":[82],"A":[83],"key":[84],"requirement":[85],"for":[86,100,116,141,179],"effectiveness":[88],"these":[90],"tools,":[91],"is":[93],"availability":[95],"accurate":[97],"analytical":[98,165],"models":[99,105,122,166,196],"area.":[103],"Such":[104],"unfortunately":[107],"not":[108],"understood":[113],"those":[115],"communication":[118],"fabrics.":[119],"Further,":[120],"simplistic":[121],"may":[123],"turn":[124],"out":[125],"be":[127,223],"totally":[128],"inaccurate":[129],"when":[130],"applied":[131,224],"wire":[133],"dominated":[134],"architectures;":[135],"this":[136,152],"observation":[137],"demands":[138],"at":[139],"least":[140],"model":[143],"validation":[144],"step":[145],"against":[146],"placed":[147,226],"routed":[149,228],"devices.":[150],"In":[151],"work,":[153],"given":[154],"reference":[157],"architecture,":[158],"we":[159],"present":[160],"flow":[162],"devise":[164],"occupation":[169],"consumption":[172],"switches,":[175],"propose":[177],"strategies":[178],"coefficient":[180],"characterization":[181],"which":[182],"have":[183],"different":[184],"tradeoffs":[185],"terms":[187],"accuracy":[189,214],"modeling":[192],"activity":[193],"effort.":[194],"The":[195],"parameterized":[198],"on":[199],"several":[200],"architectural,":[201],"synthesis-related,":[202],"traffic":[204],"variables,":[205],"resulting":[206],"maximum":[208],"flexibility.":[209],"We":[210],"finally":[211],"assess":[212],"models,":[217],"checking":[218],"whether":[219],"can":[221],"also":[222],"blocks.":[230]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":4}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
