{"id":"https://openalex.org/W2031837447","doi":"https://doi.org/10.1155/2001/92781","title":"Two\u2010dimensional Placement Using Tabu Search","display_name":"Two\u2010dimensional Placement Using Tabu Search","publication_year":1999,"publication_date":"1999-12-03","ids":{"openalex":"https://openalex.org/W2031837447","doi":"https://doi.org/10.1155/2001/92781","mag":"2031837447"},"language":"en","primary_location":{"id":"doi:10.1155/2001/92781","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/92781","pdf_url":"https://downloads.hindawi.com/archive/2001/092781.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2001/092781.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031863054","display_name":"John M. Emmert","orcid":"https://orcid.org/0000-0002-6074-535X"},"institutions":[{"id":"https://openalex.org/I102149020","display_name":"University of North Carolina at Charlotte","ror":"https://ror.org/04dawnj30","country_code":"US","type":"education","lineage":["https://openalex.org/I102149020"]},{"id":"https://openalex.org/I143302722","display_name":"University of Kentucky","ror":"https://ror.org/02k3smh20","country_code":"US","type":"education","lineage":["https://openalex.org/I143302722"]},{"id":"https://openalex.org/I4210157642","display_name":"Institute of Automation","ror":"https://ror.org/056qj1t15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210157642","https://openalex.org/I78650965"]}],"countries":["DE","US"],"is_corresponding":true,"raw_author_name":"John M. Emmert","raw_affiliation_strings":["Design Automation and Test Laboratory, Dept. of ECE, University of North Carolina","#N##TAB##TAB##TAB##TAB# Univ. of Kentucky#N##TAB##TAB##TAB#","Design Automation and Test Laboratory, Dept. of ECE, University of North Carolina, Charlotte 28223-0001, NC, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Automation and Test Laboratory, Dept. of ECE, University of North Carolina","institution_ids":["https://openalex.org/I4210157642"]},{"raw_affiliation_string":"#N##TAB##TAB##TAB##TAB# Univ. of Kentucky#N##TAB##TAB##TAB#","institution_ids":["https://openalex.org/I143302722"]},{"raw_affiliation_string":"Design Automation and Test Laboratory, Dept. of ECE, University of North Carolina, Charlotte 28223-0001, NC, USA","institution_ids":["https://openalex.org/I102149020"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069692759","display_name":"Dinesh Bhatia","orcid":"https://orcid.org/0000-0002-5019-7417"},"institutions":[{"id":"https://openalex.org/I4210157642","display_name":"Institute of Automation","ror":"https://ror.org/056qj1t15","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210157642","https://openalex.org/I78650965"]},{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["DE","US"],"is_corresponding":false,"raw_author_name":"Dinesh K. Bhatia","raw_affiliation_strings":["Design Automation Laboratory, Dept. of ECECS, University of Cincinnati","Design Automation Laboratory, Dept. of ECECS, University of Cincinnati, Cincinnati 45221-0030, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Automation Laboratory, Dept. of ECECS, University of Cincinnati","institution_ids":["https://openalex.org/I4210157642"]},{"raw_affiliation_string":"Design Automation Laboratory, Dept. of ECECS, University of Cincinnati, Cincinnati 45221-0030, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5031863054"],"corresponding_institution_ids":["https://openalex.org/I102149020","https://openalex.org/I143302722","https://openalex.org/I4210157642"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11052663,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"12","issue":"1","first_page":"13","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10533","display_name":"Teaching and Learning Programming","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1706","display_name":"Computer Science Applications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/tabu-search","display_name":"Tabu search","score":0.8812193870544434},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4973013699054718},{"id":"https://openalex.org/keywords/guided-local-search","display_name":"Guided Local Search","score":0.4770975708961487},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.46872270107269287},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.34478312730789185},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34001463651657104}],"concepts":[{"id":"https://openalex.org/C123370116","wikidata":"https://www.wikidata.org/wiki/Q1424540","display_name":"Tabu search","level":2,"score":0.8812193870544434},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4973013699054718},{"id":"https://openalex.org/C90189156","wikidata":"https://www.wikidata.org/wiki/Q5615481","display_name":"Guided Local Search","level":3,"score":0.4770975708961487},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.46872270107269287},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.34478312730789185},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34001463651657104}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/2001/92781","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/92781","pdf_url":"https://downloads.hindawi.com/archive/2001/092781.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:7794d94d0c244fee89a9a40508133777","is_oa":false,"landing_page_url":"https://doaj.org/article/7794d94d0c244fee89a9a40508133777","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Vol 12, Iss 1, Pp 13-23 (2001)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2001/92781","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/92781","pdf_url":"https://downloads.hindawi.com/archive/2001/092781.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2031837447.pdf","grobid_xml":"https://content.openalex.org/works/W2031837447.grobid-xml"},"referenced_works_count":31,"referenced_works":["https://openalex.org/W1499164988","https://openalex.org/W1960552015","https://openalex.org/W1984693366","https://openalex.org/W2028789485","https://openalex.org/W2067446923","https://openalex.org/W2069937662","https://openalex.org/W2076639376","https://openalex.org/W2098243659","https://openalex.org/W2099536895","https://openalex.org/W2125979848","https://openalex.org/W2139637699","https://openalex.org/W2150375057","https://openalex.org/W2153380648","https://openalex.org/W2160474882","https://openalex.org/W2171470054","https://openalex.org/W2171850209","https://openalex.org/W2293958994","https://openalex.org/W2339500526","https://openalex.org/W2917685881","https://openalex.org/W3023706999","https://openalex.org/W4230225091","https://openalex.org/W4231123287","https://openalex.org/W4233928430","https://openalex.org/W4248471872","https://openalex.org/W4250385255","https://openalex.org/W4254416875","https://openalex.org/W6646353350","https://openalex.org/W6682929092","https://openalex.org/W6683889123","https://openalex.org/W6697270478","https://openalex.org/W6760466160"],"related_works":["https://openalex.org/W1987877777","https://openalex.org/W2370323645","https://openalex.org/W4247343174","https://openalex.org/W2168643831","https://openalex.org/W4243772339","https://openalex.org/W1559717033","https://openalex.org/W2139271550","https://openalex.org/W2075514833","https://openalex.org/W192716354","https://openalex.org/W3203276095"],"abstract_inverted_index":{"Search":[0],"based":[1,33,59,112,124],"placement":[2,54,63,86],"of":[3,46,87,134,141],"modules":[4,38],"is":[5,13,49,58,68,83],"an":[6,129],"important":[7],"problem":[8],"in":[9],"VLSI":[10],"design.":[11],"It":[12],"always":[14],"desired":[15],"that":[16],"the":[17,47,53,75],"search":[18,32,116],"should":[19],"converge":[20],"quickly":[21],"to":[22,36,50,101,120,145],"a":[23,30,40,61],"high":[24],"quality":[25,140],"solution.":[26],"This":[27],"paper":[28],"presents":[29],"tabu":[31,115],"optimization":[34],"technique":[35,48,57,82,117],"place":[37],"on":[39,60,91,139],"regular":[41],"two\u2010dimensional":[42],"array.":[43],"The":[44,56,65,81,114],"goal":[45],"speed":[51],"up":[52],"process.":[55],"two\u2010step":[62],"strategy.":[64],"first":[66],"step":[67,77],"targeted":[69],"toward":[70],"improving":[71],"circuit":[72,79],"routability":[73],"and":[74,108,126],"second":[76],"addresses":[78],"performance.":[80],"demonstrated":[84],"through":[85],"several":[88],"benchmark":[89],"circuits":[90],"academic":[92],"as":[93,95],"well":[94],"commercial":[96,105,146],"FPGAs.":[97],"Results":[98],"are":[99],"compared":[100,144],"placements":[102],"generated":[103],"by":[104],"CAE":[106],"tools":[107],"published":[109,121],"simulated":[110,122],"annealing":[111,123],"techniques.":[113],"compares":[118],"favorably":[119],"techniques,":[125],"it":[127],"demonstrates":[128],"average":[130],"execution":[131],"time":[132],"speedup":[133],"20":[135],"with":[136],"no":[137],"impact":[138],"results":[142],"when":[143],"tools.":[147]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2025-10-10T00:00:00"}
