{"id":"https://openalex.org/W2085856286","doi":"https://doi.org/10.1155/2001/82129","title":"An Instruction\u2010Level Power Analysis Model with Data Dependency","display_name":"An Instruction\u2010Level Power Analysis Model with Data Dependency","publication_year":2000,"publication_date":"2000-08-03","ids":{"openalex":"https://openalex.org/W2085856286","doi":"https://doi.org/10.1155/2001/82129","mag":"2085856286"},"language":"en","primary_location":{"id":"doi:10.1155/2001/82129","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/82129","pdf_url":"https://downloads.hindawi.com/archive/2001/082129.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2001/082129.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054750044","display_name":"Giuseppe Ascia","orcid":"https://orcid.org/0000-0001-7452-5828"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Giuseppe Ascia","raw_affiliation_strings":["Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Universit\u00e0 di Catania, V.le. A. Doria, Catania 6\u201395125"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Universit\u00e0 di Catania, V.le. A. Doria, Catania 6\u201395125","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101778204","display_name":"Vincenzo Catania","orcid":"https://orcid.org/0000-0002-5040-3540"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Vincenzo Catania","raw_affiliation_strings":["Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Universit\u00e0 di Catania, V.le. A. Doria, Catania 6\u201395125"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Universit\u00e0 di Catania, V.le. A. Doria, Catania 6\u201395125","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010989172","display_name":"Maurizio Palesi","orcid":"https://orcid.org/0000-0003-3129-0664"},"institutions":[{"id":"https://openalex.org/I39063666","display_name":"University of Catania","ror":"https://ror.org/03a64bh57","country_code":"IT","type":"education","lineage":["https://openalex.org/I39063666"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Maurizio Palesi","raw_affiliation_strings":["Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Universit\u00e0 di Catania, V.le. A. Doria, Catania 6\u201395125"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, Universit\u00e0 di Catania, V.le. A. Doria, Catania 6\u201395125","institution_ids":["https://openalex.org/I39063666"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046429934","display_name":"Davide Sarta","orcid":null},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Davide Sarta","raw_affiliation_strings":["STMicroelectronics, Stradale Primosole, Catania 95100"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Stradale Primosole, Catania 95100","institution_ids":["https://openalex.org/I131827901"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5054750044"],"corresponding_institution_ids":["https://openalex.org/I39063666"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":10,"citation_normalized_percentile":{"value":0.16236998,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"12","issue":"2","first_page":"245","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7496575117111206},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7280458807945251},{"id":"https://openalex.org/keywords/dependency","display_name":"Dependency (UML)","score":0.6517963409423828},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.619369626045227},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5661150217056274},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5570142865180969},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.47508755326271057},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.46245670318603516},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.4283261299133301},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3683182895183563},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3473818898200989},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34206998348236084},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3005177974700928},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11705988645553589},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.11018425226211548}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7496575117111206},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7280458807945251},{"id":"https://openalex.org/C19768560","wikidata":"https://www.wikidata.org/wiki/Q320727","display_name":"Dependency (UML)","level":2,"score":0.6517963409423828},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.619369626045227},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5661150217056274},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5570142865180969},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.47508755326271057},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.46245670318603516},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.4283261299133301},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3683182895183563},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3473818898200989},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34206998348236084},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3005177974700928},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11705988645553589},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.11018425226211548},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1155/2001/82129","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/82129","pdf_url":"https://downloads.hindawi.com/archive/2001/082129.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.97.8185","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.97.8185","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.diit.unict.it/users/mpalesi/DOWNLOAD/vlsidesign.pdf","raw_type":"text"},{"id":"pmh:oai:doaj.org/article:4b3b28e820ca4fcf9884356955e5fa2d","is_oa":false,"landing_page_url":"https://doaj.org/article/4b3b28e820ca4fcf9884356955e5fa2d","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Vol 12, Iss 2, Pp 245-273 (2001)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2001/82129","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/82129","pdf_url":"https://downloads.hindawi.com/archive/2001/082129.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2085856286.pdf","grobid_xml":"https://content.openalex.org/works/W2085856286.grobid-xml"},"referenced_works_count":39,"referenced_works":["https://openalex.org/W1833472860","https://openalex.org/W1913908537","https://openalex.org/W1972705270","https://openalex.org/W1993408465","https://openalex.org/W2001215920","https://openalex.org/W2020117734","https://openalex.org/W2036429211","https://openalex.org/W2043165230","https://openalex.org/W2053325937","https://openalex.org/W2097159002","https://openalex.org/W2099315024","https://openalex.org/W2103402005","https://openalex.org/W2114893176","https://openalex.org/W2115283580","https://openalex.org/W2116629722","https://openalex.org/W2121382240","https://openalex.org/W2129663297","https://openalex.org/W2145092051","https://openalex.org/W2148415652","https://openalex.org/W2155063924","https://openalex.org/W2157435683","https://openalex.org/W2161280215","https://openalex.org/W2165072326","https://openalex.org/W2169826970","https://openalex.org/W2615865818","https://openalex.org/W2952880697","https://openalex.org/W3141828823","https://openalex.org/W4230282966","https://openalex.org/W4242164461","https://openalex.org/W4244980230","https://openalex.org/W4246993084","https://openalex.org/W4249862477","https://openalex.org/W4255749601","https://openalex.org/W4299621883","https://openalex.org/W6639860915","https://openalex.org/W6648490476","https://openalex.org/W6650728892","https://openalex.org/W6682257490","https://openalex.org/W6684493930"],"related_works":["https://openalex.org/W2545964721","https://openalex.org/W2538644970","https://openalex.org/W4376881175","https://openalex.org/W2204566833","https://openalex.org/W4310584696","https://openalex.org/W4237840813","https://openalex.org/W2128502296","https://openalex.org/W4385730960","https://openalex.org/W2503229030","https://openalex.org/W2993622674"],"abstract_inverted_index":{"Power":[0],"constraints":[1],"are":[2,33,41],"becoming":[3,24],"a":[4,49,55,60],"critical":[5],"design":[6],"issue":[7],"in":[8,47,83,113,126],"the":[9,72,105,127,130],"field":[10],"of":[11,17,39,104,129],"portable":[12],"microprocessor":[13],"systems.":[14],"The":[15,90],"impact":[16],"software":[18,46,115],"on":[19,54],"overall":[20],"system":[21],"power":[22,63,116],"is":[23,52,66,69,122],"increasingly":[25],"important":[26],"as":[27,35],"more":[28,30],"and":[29,44,87],"digital":[31],"applications":[32],"implemented":[34],"embedded":[36],"systems,":[37],"part":[38,45],"which":[40,48,121],"hardware":[42],"(ASICs)":[43],"specific":[50],"application":[51],"executed":[53],"processor.":[56,102],"In":[57],"this":[58],"paper,":[59],"data\u2010dependent":[61,91,106],"instruction\u2010level":[62],"analysis":[64],"model":[65,75,92,107],"presented.":[67],"It":[68],"compared":[70],"with":[71],"average":[73],"cost":[74],"proposed":[76],"by":[77],"Tiwari":[78],"et":[79],"al":[80],".":[81],"[1]":[82],"both":[84],"estimation":[85],"accuracy":[86],"characterisation":[88],"time.":[89],"can":[93],"be":[94,97],"generalised":[95],"to":[96,99],"applied":[98],"generic":[100],"RISC":[101],"Application":[103],"we":[108],"propose":[109],"sensibly":[110],"reduces":[111],"errors":[112],"estimating":[114],"consumption":[117],"per":[118],"clock":[119],"cycle":[120],"lower":[123],"than":[124],"10%,":[125],"case":[128],"ST20\u2010C2P":[131],"core.":[132]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
