{"id":"https://openalex.org/W2135178267","doi":"https://doi.org/10.1155/2001/79703","title":"Effect of Reverse Body Bias on Current Testing of 0.18 \u03bcm Gates","display_name":"Effect of Reverse Body Bias on Current Testing of 0.18 \u03bcm Gates","publication_year":2000,"publication_date":"2000-09-11","ids":{"openalex":"https://openalex.org/W2135178267","doi":"https://doi.org/10.1155/2001/79703","mag":"2135178267"},"language":"en","primary_location":{"id":"doi:10.1155/2001/79703","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/79703","pdf_url":"https://downloads.hindawi.com/archive/2001/079703.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2001/079703.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100373344","display_name":"Xiaomei Liu","orcid":"https://orcid.org/0000-0002-7011-4009"},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaomei Liu","raw_affiliation_strings":["Electrical Engineering Department, Santa Clara University, 500 El Camino Real"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Santa Clara University, 500 El Camino Real","institution_ids":["https://openalex.org/I16269868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057637319","display_name":"Prachi Sathe","orcid":null},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prachi Sathe","raw_affiliation_strings":["Electrical Engineering Department, Santa Clara University, 500 El Camino Real"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Santa Clara University, 500 El Camino Real","institution_ids":["https://openalex.org/I16269868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109801605","display_name":"S. Mourad","orcid":null},"institutions":[{"id":"https://openalex.org/I16269868","display_name":"Santa Clara University","ror":"https://ror.org/03ypqe447","country_code":"US","type":"education","lineage":["https://openalex.org/I16269868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Samiha Mourad","raw_affiliation_strings":["Electrical Engineering Department, Santa Clara University, 500 El Camino Real"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Santa Clara University, 500 El Camino Real","institution_ids":["https://openalex.org/I16269868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5109801605"],"corresponding_institution_ids":["https://openalex.org/I16269868"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18100167,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"12","issue":"4","first_page":"501","last_page":"513"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7744121551513672},{"id":"https://openalex.org/keywords/reverse-bias","display_name":"Reverse bias","score":0.7400103807449341},{"id":"https://openalex.org/keywords/iddq-testing","display_name":"Iddq testing","score":0.6980310082435608},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6501894593238831},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5214735269546509},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.49524131417274475},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.48516613245010376},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4681409001350403},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4235965609550476},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.40385866165161133},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4006921052932739},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3531284034252167},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.26813292503356934},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26101458072662354}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7744121551513672},{"id":"https://openalex.org/C2987974824","wikidata":"https://www.wikidata.org/wiki/Q176300","display_name":"Reverse bias","level":3,"score":0.7400103807449341},{"id":"https://openalex.org/C206678392","wikidata":"https://www.wikidata.org/wiki/Q5987815","display_name":"Iddq testing","level":3,"score":0.6980310082435608},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6501894593238831},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5214735269546509},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.49524131417274475},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.48516613245010376},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4681409001350403},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4235965609550476},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.40385866165161133},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4006921052932739},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3531284034252167},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.26813292503356934},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26101458072662354}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2001/79703","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/79703","pdf_url":"https://downloads.hindawi.com/archive/2001/079703.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2001/79703","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2001/79703","pdf_url":"https://downloads.hindawi.com/archive/2001/079703.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5799999833106995}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2135178267.pdf","grobid_xml":"https://content.openalex.org/works/W2135178267.grobid-xml"},"referenced_works_count":36,"referenced_works":["https://openalex.org/W122496158","https://openalex.org/W1527363716","https://openalex.org/W1531892350","https://openalex.org/W1680657443","https://openalex.org/W1913711070","https://openalex.org/W1980752911","https://openalex.org/W1982756257","https://openalex.org/W2003545114","https://openalex.org/W2012535699","https://openalex.org/W2031457512","https://openalex.org/W2032838772","https://openalex.org/W2051431054","https://openalex.org/W2059510494","https://openalex.org/W2100837687","https://openalex.org/W2101406500","https://openalex.org/W2108049334","https://openalex.org/W2115706095","https://openalex.org/W2116070420","https://openalex.org/W2122552745","https://openalex.org/W2133493135","https://openalex.org/W2147198689","https://openalex.org/W2158581741","https://openalex.org/W2165523058","https://openalex.org/W2167138208","https://openalex.org/W2169216177","https://openalex.org/W3104443652","https://openalex.org/W4232164942","https://openalex.org/W4247409213","https://openalex.org/W4254793419","https://openalex.org/W6603492654","https://openalex.org/W6604992875","https://openalex.org/W6637142179","https://openalex.org/W6653653311","https://openalex.org/W6658218365","https://openalex.org/W6674893155","https://openalex.org/W6675113688"],"related_works":["https://openalex.org/W4383652277","https://openalex.org/W2591624843","https://openalex.org/W1619670034","https://openalex.org/W2103878286","https://openalex.org/W2135178267","https://openalex.org/W2004855197","https://openalex.org/W2530714850","https://openalex.org/W1979450039","https://openalex.org/W2104224956","https://openalex.org/W2007571448"],"abstract_inverted_index":{"Systematic":[0],"investigations":[1],"on":[2,34],"defect\u2010free":[3,61,85,113,157],"I":[4,26,42,62,86,114,125,134,158],"DDQ":[5,27,43,63,87,115,126,135,159],"in":[6,84],"deep":[7],"submicron":[8],"CMOS":[9,39,46,140],"with":[10],"reverse":[11,31,55,107,151,163],"body":[12,32,56,108,152],"bias":[13,33,57,109,153,164],"were":[14,49],"performed":[15],"by":[16],"SPICE":[17],"simulation":[18],"towards":[19],"an":[20,149],"attempt":[21],"to":[22,118,177,180,185],"improve":[23],"resolution":[24],"of":[25,30,37,44,64,137],"measurement.":[28],"Effects":[29],"off\u2010state":[35],"leakage":[36],"scaled":[38],"devices":[40,69],"and":[41,70,96,172,182],"typical":[45,65],"circuit":[47,176],"cells":[48],"investigated.":[50],"It":[51,142],"was":[52,88,143],"found":[53,144],"that":[54,106,145,154],"can":[58],"effectively":[59],"reduce":[60],"0.18":[66,138],"\u03bcm":[67,139],"technology":[68,183],"logic":[71],"gates":[72],"while":[73],"the":[74,91,99,112,119,156,168],"faulty":[75],"current":[76,127],"is":[77],"not":[78],"as":[79,90,98,167],"much":[80],"reduced.":[81],"The":[82,161],"reduction":[83],"enhanced":[89],"device":[92],"temperature":[93,100,169],"went":[94,101,170],"up":[95],"diminishes":[97],"down.":[102],"Further":[103],"investigation":[104],"showed":[105],"also":[110],"makes":[111],"less":[116],"sensitive":[117],"input":[120],"state;":[121],"therefore,":[122],"a":[123],"single":[124],"threshold":[128],"might":[129,147,173],"still":[130],"be":[131],"used":[132],"for":[133],"testing":[136],"circuits.":[141],"there":[146],"exist":[148],"optimal":[150,162],"minimized":[155],"current.":[160],"value":[165],"decreases":[166],"down":[171],"vary":[174],"from":[175],"circuit,":[178],"process":[179],"process,":[181],"generation":[184],"generation.":[186]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}