{"id":"https://openalex.org/W2005243862","doi":"https://doi.org/10.1155/2000/71046","title":"An Edge\u2010endpoint\u2010based Configurable HardwareArchitecture for VLSI Layout Design Rule Checking","display_name":"An Edge\u2010endpoint\u2010based Configurable HardwareArchitecture for VLSI Layout Design Rule Checking","publication_year":1999,"publication_date":"1999-10-01","ids":{"openalex":"https://openalex.org/W2005243862","doi":"https://doi.org/10.1155/2000/71046","mag":"2005243862"},"language":"en","primary_location":{"id":"doi:10.1155/2000/71046","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/71046","pdf_url":"https://downloads.hindawi.com/archive/2000/071046.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2000/071046.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103537715","display_name":"Zhen Luo","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]},{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN","US"],"is_corresponding":false,"raw_author_name":"Zhen Luo","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University","Peking University","Princeton University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Peking University","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Princeton University","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002015508","display_name":"Margaret Martonosi","orcid":"https://orcid.org/0000-0001-9683-8032"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]},{"id":"https://openalex.org/I29955533","display_name":"Center for Information Technology","ror":"https://ror.org/03jh5a977","country_code":"US","type":"facility","lineage":["https://openalex.org/I1299022934","https://openalex.org/I1299303238","https://openalex.org/I29955533"]},{"id":"https://openalex.org/I4210094144","display_name":"Environmental Institute","ror":"https://ror.org/00n893e13","country_code":"SK","type":"company","lineage":["https://openalex.org/I4210094144"]}],"countries":["SK","US"],"is_corresponding":false,"raw_author_name":"Margaret Martonosi","raw_affiliation_strings":["Department of Electrical Engineering, Princeton University","Center for Information Technology Policy","Princeton Environmental Institute"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Princeton University","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Center for Information Technology Policy","institution_ids":["https://openalex.org/I29955533"]},{"raw_affiliation_string":"Princeton Environmental Institute","institution_ids":["https://openalex.org/I4210094144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060336834","display_name":"Pranav Ashar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210107830","display_name":"Nerve Centre","ror":"https://ror.org/01r7ewj84","country_code":"GB","type":"nonprofit","lineage":["https://openalex.org/I4210107830"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Pranav Ashar","raw_affiliation_strings":["NEC CCRL","University of California at Berkeley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NEC CCRL","institution_ids":["https://openalex.org/I4210107830"]},{"raw_affiliation_string":"University of California at Berkeley","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":4,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4013,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.67834793,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":96},"biblio":{"volume":"10","issue":"3","first_page":"249","last_page":"263"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7286072969436646},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7077056169509888},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6552746295928955},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6415140628814697},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5967854261398315},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5601078867912292},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5105422735214233},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5001816749572754},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49033522605895996},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4864673316478729},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.4419710040092468},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43786105513572693},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4183926582336426},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11208254098892212},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09809109568595886}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7286072969436646},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7077056169509888},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6552746295928955},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6415140628814697},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5967854261398315},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5601078867912292},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5105422735214233},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5001816749572754},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49033522605895996},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4864673316478729},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.4419710040092468},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43786105513572693},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4183926582336426},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11208254098892212},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09809109568595886},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1155/2000/71046","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/71046","pdf_url":"https://downloads.hindawi.com/archive/2000/071046.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:4f23c72b17b74920aaaff2c779470762","is_oa":false,"landing_page_url":"https://doaj.org/article/4f23c72b17b74920aaaff2c779470762","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Vol 10, Iss 3, Pp 249-263 (2000)","raw_type":"article"},{"id":"pmh:oai:doaj.org/article:feabf5a67b1840d5b91e9bd399dbe330","is_oa":false,"landing_page_url":"https://doaj.org/article/feabf5a67b1840d5b91e9bd399dbe330","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Vol 10, Iss 3, Pp 249-263 (2000)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2000/71046","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/71046","pdf_url":"https://downloads.hindawi.com/archive/2000/071046.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2005243862.pdf","grobid_xml":"https://content.openalex.org/works/W2005243862.grobid-xml"},"referenced_works_count":13,"referenced_works":["https://openalex.org/W1979555000","https://openalex.org/W1994813238","https://openalex.org/W2101497303","https://openalex.org/W2125076291","https://openalex.org/W2161070735","https://openalex.org/W2170581017","https://openalex.org/W4206401860","https://openalex.org/W4234388789","https://openalex.org/W4240048567","https://openalex.org/W4245299340","https://openalex.org/W4249362752","https://openalex.org/W6663352504","https://openalex.org/W6669051336"],"related_works":["https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2984236338","https://openalex.org/W1967938402","https://openalex.org/W2134640991","https://openalex.org/W2386041993","https://openalex.org/W3027318491","https://openalex.org/W1608572506","https://openalex.org/W2160474882","https://openalex.org/W2141823036"],"abstract_inverted_index":{"Previous":[0],"efforts":[1],"to":[2,23,46,61,98,139],"build":[3,24],"hardware":[4,44,142],"accelerators":[5],"for":[6,77,87,104],"VLSI":[7],"layout":[8],"Design":[9],"Rule":[10],"Checking":[11],"(DRC)":[12],"were":[13],"hobbled":[14],"by":[15,94],"the":[16,58,63,141],"fact":[17],"that":[18],"it":[19],"is":[20],"often":[21],"impractical":[22],"a":[25,42,83,99,116,135,147],"different":[26],"rulechecking":[27],"ASIC":[28],"each":[29],"time":[30],"design":[31,102,112],"rules":[32,67,103],"or":[33,68],"fabrication":[34],"processes":[35,69],"change.":[36,70],"In":[37],"this":[38,96],"paper,":[39],"we":[40],"propose":[41],"configurable":[43],"approach":[45,93],"DRC.":[47,88],"It":[48],"can":[49],"garner":[50],"impressive":[51],"speedups":[52,124],"over":[53,129],"software":[54,130],"approaches,":[55],"while":[56],"retaining":[57],"flexibility":[59],"needed":[60],"change":[62],"rule":[64,113],"checker":[65],"as":[66],"Our":[71],"work":[72],"proposes":[73],"an":[74],"edge\u2010endpoints\u2010based":[75],"method":[76],"performing":[78],"Manhattan":[79],"geometry":[80],"checking":[81],"and":[82,121,144],"general":[84],"scalable":[85],"architecture":[86,97],"We":[89,108,132],"then":[90],"demonstrate":[91],"our":[92],"applying":[95],"set":[100],"of":[101,127,150],"MOSIS":[105],"SCN4N_SUB":[106],"process.":[107],"have":[109,133,145],"implemented":[110],"several":[111],"checks":[114],"within":[115],"single":[117],"Xilinx":[118],"XC4013":[119],"FPGA":[120],"demonstrated":[122],"overall":[123],"in":[125],"excess":[126],"25X":[128],"methods.":[131],"used":[134],"Compaq":[136],"Pamette":[137],"board":[138],"do":[140],"prototyping":[143],"achieved":[146],"clock":[148],"rate":[149],"33":[151],"MHz.":[152]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2}],"updated_date":"2026-08-15T07:11:24.734988","created_date":"2025-10-10T00:00:00"}
