{"id":"https://openalex.org/W1968556013","doi":"https://doi.org/10.1155/2000/69148","title":"Design and Analysis of Radix\u20108/4/2 64b/32b Integer Divider Using COMPASS Cell Library","display_name":"Design and Analysis of Radix\u20108/4/2 64b/32b Integer Divider Using COMPASS Cell Library","publication_year":1999,"publication_date":"1999-09-24","ids":{"openalex":"https://openalex.org/W1968556013","doi":"https://doi.org/10.1155/2000/69148","mag":"1968556013"},"language":"en","primary_location":{"id":"doi:10.1155/2000/69148","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/69148","pdf_url":"https://downloads.hindawi.com/archive/2000/069148.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2000/069148.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077220045","display_name":"Chua\u2010Chin Wang","orcid":"https://orcid.org/0000-0002-2426-2879"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chua-Chin Wang","raw_affiliation_strings":["Department of Electrical Engineering, National Sun Yat-Sen University"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Sun Yat-Sen University","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091460546","display_name":"Chenn\u2010Jung Huang","orcid":"https://orcid.org/0000-0002-0174-0831"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chenn-Jung Huang","raw_affiliation_strings":["Department of Electrical Engineering, National Sun Yat-Sen University"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Sun Yat-Sen University","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003818825","display_name":"I-Yen Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"I-Yen Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Sun Yat-Sen University"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Sun Yat-Sen University","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5077220045"],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":0.4708,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61311534,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"11","issue":"4","first_page":"331","last_page":"338"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/division","display_name":"Division (mathematics)","score":0.7519725561141968},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6861145496368408},{"id":"https://openalex.org/keywords/radix","display_name":"Radix (gastropod)","score":0.5966961979866028},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5601803064346313},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.5550537109375},{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.5466757416725159},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.49908924102783203},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.45448800921440125},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4155060052871704},{"id":"https://openalex.org/keywords/current-divider","display_name":"Current divider","score":0.41351786255836487},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.332520991563797},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.26819878816604614},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.13524064421653748},{"id":"https://openalex.org/keywords/power-dividers-and-directional-couplers","display_name":"Power dividers and directional couplers","score":0.0926128625869751},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07960176467895508},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.0656619668006897},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06558215618133545}],"concepts":[{"id":"https://openalex.org/C60798267","wikidata":"https://www.wikidata.org/wiki/Q1226939","display_name":"Division (mathematics)","level":2,"score":0.7519725561141968},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6861145496368408},{"id":"https://openalex.org/C2779091547","wikidata":"https://www.wikidata.org/wiki/Q287565","display_name":"Radix (gastropod)","level":2,"score":0.5966961979866028},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5601803064346313},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.5550537109375},{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.5466757416725159},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.49908924102783203},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.45448800921440125},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4155060052871704},{"id":"https://openalex.org/C97264828","wikidata":"https://www.wikidata.org/wiki/Q4157078","display_name":"Current divider","level":4,"score":0.41351786255836487},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.332520991563797},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.26819878816604614},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.13524064421653748},{"id":"https://openalex.org/C202988678","wikidata":"https://www.wikidata.org/wiki/Q1417986","display_name":"Power dividers and directional couplers","level":2,"score":0.0926128625869751},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07960176467895508},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0656619668006897},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06558215618133545},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C59822182","wikidata":"https://www.wikidata.org/wiki/Q441","display_name":"Botany","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/2000/69148","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/69148","pdf_url":"https://downloads.hindawi.com/archive/2000/069148.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:f36880c1d11641dbbd79437c5d08aca3","is_oa":true,"landing_page_url":"https://doaj.org/article/f36880c1d11641dbbd79437c5d08aca3","pdf_url":null,"source":{"id":"https://openalex.org/S112646816","display_name":"SHILAP Revista de lepidopterolog\u00eda","issn_l":"0300-5267","issn":["0300-5267","2340-4078"],"is_oa":true,"is_in_doaj":true,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Vol 11, Iss 4, Pp 331-338 (2000)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2000/69148","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/69148","pdf_url":"https://downloads.hindawi.com/archive/2000/069148.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1968556013.pdf","grobid_xml":"https://content.openalex.org/works/W1968556013.grobid-xml"},"referenced_works_count":9,"referenced_works":["https://openalex.org/W198483250","https://openalex.org/W1513550257","https://openalex.org/W1571288491","https://openalex.org/W1571629760","https://openalex.org/W1578458555","https://openalex.org/W1586616317","https://openalex.org/W1601585824","https://openalex.org/W6608130901","https://openalex.org/W6635281863"],"related_works":["https://openalex.org/W1968508814","https://openalex.org/W1980674890","https://openalex.org/W2278825048","https://openalex.org/W2119913708","https://openalex.org/W1544944064","https://openalex.org/W2366057978","https://openalex.org/W2022195966","https://openalex.org/W3144043557","https://openalex.org/W2786631194","https://openalex.org/W2013143169"],"abstract_inverted_index":{"A":[0],"high":[1],"speed":[2],"64b/32b":[3],"integer":[4,30],"divider":[5,41,105],"employing":[6,77],"digit\u2010recurrence":[7],"division":[8,46],"method":[9],"and":[10,85],"the":[11,25,28,33,39,49,60,64,102],"on\u2010the\u2010fly":[12],"conversion":[13],"algorithm,":[14],"wherein":[15],"a":[16,43,98],"fast":[17],"normalizer":[18],"is":[19,22,56,69,97],"included,":[20],"which":[21],"used":[23],"as":[24],"pre\u2010processor":[26],"of":[27,35,48,63],"proposed":[29,40],"divider.":[31,65],"For":[32],"sake":[34],"enhancing":[36],"throughput":[37],"rate,":[38],"uses":[42],"mixed":[44],"radix\u20108/4/2":[45],"instead":[47],"traditional":[50],"radix\u20102":[51],"division.":[52],"On\u2010the\u2010fly":[53],"remainder":[54],"adjustment":[55],"also":[57],"realized":[58],"in":[59,71],"converter":[61],"module":[62],"The":[66,90],"entire":[67],"design":[68,96],"written":[70],"Verilog":[72],"HDL":[73],"(hardware":[74],"description":[75],"language)":[76],"COMPASS":[78],"0.6":[79],"\u03bcm":[80],"1P3M":[81],"cell":[82],"library":[83],"(V3.0),":[84],"then":[86],"synthesized":[87],"by":[88],"SYNOPSYS.":[89],"simulation":[91],"results":[92],"indicate":[93],"that":[94],"our":[95],"better":[99],"option":[100],"than":[101],"existing":[103],"long":[104],"designs.":[106]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}