{"id":"https://openalex.org/W4241944886","doi":"https://doi.org/10.1155/2000/24749","title":"Guest Editorial","display_name":"Guest Editorial","publication_year":1999,"publication_date":"1999-10-01","ids":{"openalex":"https://openalex.org/W4241944886","doi":"https://doi.org/10.1155/2000/24749"},"language":"en","primary_location":{"id":"doi:10.1155/2000/24749","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/24749","pdf_url":"https://downloads.hindawi.com/archive/2000/024749.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"editorial","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2000/024749.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046909633","display_name":"Jack Jean","orcid":null},"institutions":[{"id":"https://openalex.org/I19648265","display_name":"Wright State University","ror":"https://ror.org/04qk6pt94","country_code":"US","type":"education","lineage":["https://openalex.org/I19648265"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jack Jean","raw_affiliation_strings":["aWright State University; bHoneywell Technology Center"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"aWright State University; bHoneywell Technology Center","institution_ids":["https://openalex.org/I19648265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103534056","display_name":"Sanjaya Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I19648265","display_name":"Wright State University","ror":"https://ror.org/04qk6pt94","country_code":"US","type":"education","lineage":["https://openalex.org/I19648265"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjaya Kumar","raw_affiliation_strings":["aWright State University; bHoneywell Technology Center"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"aWright State University; bHoneywell Technology Center","institution_ids":["https://openalex.org/I19648265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I19648265"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":"3","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.287200003862381,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.287200003862381,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.10499999672174454,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.035599999129772186,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45471736788749695}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45471736788749695}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/2000/24749","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/24749","pdf_url":"https://downloads.hindawi.com/archive/2000/024749.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/2000/24749","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2000/24749","pdf_url":"https://downloads.hindawi.com/archive/2000/024749.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4241944886.pdf","grobid_xml":"https://content.openalex.org/works/W4241944886.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2350741829","https://openalex.org/W2130043461","https://openalex.org/W2530322880","https://openalex.org/W1596801655"],"abstract_inverted_index":{"This":[0],"special":[1,78],"issue":[2,79],"of":[3,22,29,66,86,95,145,166,186,201,207,237],"VLSI":[4,219,243],"Design":[5,222],"is":[6],"dedicated":[7],"to":[8,49,71,114,124,138,159,182],"Reconfigurable":[9],"Computing.Reconfigurable":[10],"computing":[11,97,168,209],"technologies,":[12],"such":[13,189],"as":[14,190,275],"field-programmable":[15],"gate":[16,105],"arrays":[17],"(FPGAs),":[18],"offer":[19],"the":[20,26,64,93,126,143,184,205,235],"flexibility":[21],"general-purpose":[23,54],"processors":[24],"and":[25,83,107,151,164,177,195,203,231,259],"high":[27,127],"performance":[28,52],"application-specific":[30],"integrated":[31,248],"circuits":[32],"(ASICs).FPGAs":[33],"support":[34,103,139,160,173],"static":[35],"reconfiguration,":[36],"but":[37],"recently,":[38],"there":[39],"has":[40,255],"been":[41,267],"interest":[42],"in":[43,63,92,117,131,193],"exploring":[44],"dynamic":[45,175],"reconfiguration":[46,128,141,176],"techniques.In":[47],"addition":[48],"providing":[50],"higher":[51,104],"than":[53,119],"processor":[55],"solutions,":[56],"these":[57,269],"emerging":[58,101],"technologies":[59],"provide":[60,198],"new":[61],"opportunities":[62],"development":[65,94,165],"systems":[67],"that":[68,102,290],"can":[69],"adapt":[70],"changing":[72],"conditions.The":[73],"areas":[74],"addressed":[75],"by":[76,226],"this":[77],"span":[80],"architecture,":[81],"software,":[82],"applications,":[84],"all":[85],"which":[87],"play":[88],"an":[89],"important":[90],"role":[91],"reconfigurable":[96,167,208],"systems.New":[98],"architectures":[99,134],"are":[100,135,271],"capacities":[106],"faster":[108],"speeds,":[109],"allowing":[110],"more":[111,295],"complex":[112],"algorithms":[113],"be":[115],"implemented":[116],"\"hardware\"":[118],"was":[120],"previously":[121],"possible.In":[122],"addition,":[123],"address":[125],"times":[129],"found":[130,192],"some":[132],"FPGAs,":[133],"being":[136],"developed":[137],"fast":[140],"through":[142],"use":[144],"on-chip":[146],"memory":[147],"for":[148,174,218,242,264],"storing":[149],"configurations":[150],"partial":[152],"reconfiguration.Software":[153],"includes":[154],"computer-aided":[155],"design":[156,238,244],"(CAD)":[157],"tools":[158],"partitioning,":[161],"programming,":[162],"analysis,":[163],"systems.It":[169],"also":[170],"encompasses":[171],"run-time":[172],"application":[178],"programming":[179],"interfaces":[180],"(APIs)":[181],"ease":[183],"process":[185],"implementing":[187],"applications.Applications,":[188],"those":[191],"signal":[194],"image":[196],"processing,":[197],"a":[199,283,292],"way":[200],"understanding":[202],"assessing":[204],"benefits":[206],"technology.The":[210],"first":[211],"paper":[212],"\"An":[213],"Edge-Endpoint-Based":[214],"Configurable":[215],"Hardware":[216],"Architecture":[217],"CAD":[220],"Layout":[221],"Rule":[223],"Checking\"":[224],"authored":[225],"Zhen":[227],"Luo,":[228],"Margaret":[229],"Martonosi,":[230],"Pranav":[232],"Ashar":[233],"addresses":[234],"implementation":[236],"rule":[239],"checking":[240],"(DRC)":[241],"using":[245],"configurable":[246,288],"hardware.As":[247],"circuit":[249],"die":[250],"sizes":[251],"have":[252,266],"increased,":[253],"DRC":[254,265,284],"become":[256],"extremely":[257],"time-consuming":[258],"compute-":[260],"intensive.Although":[261],"hardware":[262,289],"accelerators":[263],"proposed,":[268],"approaches":[270],"inflexible,":[272],"requiring":[273],"re-design":[274],"fabrication":[276],"processes":[277],"evolve":[278],"over":[279,297],"time.The":[280],"authors":[281],"present":[282],"approach":[285],"based":[286],"on":[287],"provides":[291],"25X":[293],"or":[294],"speedup":[296],"software":[298],"approaches.":[299]},"counts_by_year":[],"updated_date":"2026-08-15T07:11:24.734988","created_date":"2022-05-12T00:00:00"}
