{"id":"https://openalex.org/W2037473252","doi":"https://doi.org/10.1155/1999/89835","title":"Empirical Study of Block Placement by Cluster Refinement","display_name":"Empirical Study of Block Placement by Cluster Refinement","publication_year":1998,"publication_date":"1998-11-20","ids":{"openalex":"https://openalex.org/W2037473252","doi":"https://doi.org/10.1155/1999/89835","mag":"2037473252"},"language":"en","primary_location":{"id":"doi:10.1155/1999/89835","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/89835","pdf_url":"https://downloads.hindawi.com/archive/1999/089835.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1999/089835.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038610034","display_name":"Jin Xu","orcid":"https://orcid.org/0000-0001-6738-9979"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jin Xu","raw_affiliation_strings":["Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110217682","display_name":"Pei-Ning Guo","orcid":"https://orcid.org/0009-0008-1846-917X"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pei-Ning Guo","raw_affiliation_strings":["Department of Computer Science and Engineering, University of California, La Jolla, San Diego, CA 92093-0114, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of California, La Jolla, San Diego, CA 92093-0114, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039615312","display_name":"Chung\u2010Kuan Cheng","orcid":"https://orcid.org/0000-0002-9865-8390"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chung-Kuan Cheng","raw_affiliation_strings":["Department of Computer Science and Engineering, University of California, La Jolla, San Diego, CA 92093-0114, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of California, La Jolla, San Diego, CA 92093-0114, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11578226,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":"1","first_page":"71","last_page":"86"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8941984176635742},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.7664597630500793},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7035605907440186},{"id":"https://openalex.org/keywords/cluster","display_name":"Cluster (spacecraft)","score":0.6945438981056213},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.6713266372680664},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5533515810966492},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5401384830474854},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4971370995044708},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3554084300994873},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3202553391456604},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16304537653923035},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10256987810134888},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.06446480751037598},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.049856334924697876},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.04559949040412903}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8941984176635742},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.7664597630500793},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7035605907440186},{"id":"https://openalex.org/C164866538","wikidata":"https://www.wikidata.org/wiki/Q367351","display_name":"Cluster (spacecraft)","level":2,"score":0.6945438981056213},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.6713266372680664},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5533515810966492},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5401384830474854},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4971370995044708},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3554084300994873},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3202553391456604},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16304537653923035},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10256987810134888},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.06446480751037598},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.049856334924697876},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.04559949040412903},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/1999/89835","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/89835","pdf_url":"https://downloads.hindawi.com/archive/1999/089835.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/1999/89835","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/89835","pdf_url":"https://downloads.hindawi.com/archive/1999/089835.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3373283776","display_name":"Research on Rapid Prototyping Systems Using Field           Programmable Devices","funder_award_id":"9529077","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2037473252.pdf","grobid_xml":"https://content.openalex.org/works/W2037473252.grobid-xml"},"referenced_works_count":30,"referenced_works":["https://openalex.org/W1514439880","https://openalex.org/W1535529518","https://openalex.org/W1587650745","https://openalex.org/W2003309297","https://openalex.org/W2069641024","https://openalex.org/W2072974175","https://openalex.org/W2078152952","https://openalex.org/W2094042791","https://openalex.org/W2110514755","https://openalex.org/W2117179413","https://openalex.org/W2134213060","https://openalex.org/W2144473140","https://openalex.org/W2146029729","https://openalex.org/W2149066121","https://openalex.org/W2158598102","https://openalex.org/W2161375837","https://openalex.org/W2170136089","https://openalex.org/W2614099084","https://openalex.org/W4210546998","https://openalex.org/W4240309467","https://openalex.org/W4240481608","https://openalex.org/W4242900342","https://openalex.org/W4255823436","https://openalex.org/W4256007160","https://openalex.org/W6634935877","https://openalex.org/W6647952961","https://openalex.org/W6674301526","https://openalex.org/W6676972468","https://openalex.org/W6681728804","https://openalex.org/W6980659882"],"related_works":["https://openalex.org/W2030816003","https://openalex.org/W2378211422","https://openalex.org/W4239992647","https://openalex.org/W2076325756","https://openalex.org/W81423522","https://openalex.org/W2150013480","https://openalex.org/W2365454866","https://openalex.org/W2048582679","https://openalex.org/W2782226720","https://openalex.org/W3155846967"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"propose":[4],"an":[5,23],"efficient":[6],"cluster":[7,17,32],"refinement":[8,40],"approach":[9,41,63],"for":[10,26],"macro\u2010cell":[11],"placement.":[12],"The":[13],"algorithm":[14],"selects":[15],"a":[16],"of":[18,46],"blocks":[19,29],"dynamically,":[20],"and":[21],"finds":[22],"optimal":[24],"solution":[25],"all":[27],"the":[28,31,44,56,62,70,74],"in":[30,50],"simultaneously.":[33],"This":[34],"is":[35],"different":[36],"from":[37],"previous":[38],"zone":[39],"which":[42],"optimizes":[43],"allocation":[45],"one":[47],"single":[48],"block":[49],"each":[51],"operation.":[52],"Experimental":[53],"results":[54],"on":[55],"MCNC":[57],"benchmark":[58],"circuits":[59],"show":[60],"that":[61],"achieves":[64],"excellent":[65],"area":[66],"utilization":[67],"while":[68],"minimizing":[69],"wire":[71],"length":[72],"at":[73],"same":[75],"time.":[76]},"counts_by_year":[],"updated_date":"2026-08-15T07:11:24.734988","created_date":"2025-10-10T00:00:00"}
