{"id":"https://openalex.org/W2067969908","doi":"https://doi.org/10.1155/1999/54564","title":"Automatic Test Timing Assignment for RAMsUsing Linear Programming","display_name":"Automatic Test Timing Assignment for RAMsUsing Linear Programming","publication_year":1998,"publication_date":"1998-07-24","ids":{"openalex":"https://openalex.org/W2067969908","doi":"https://doi.org/10.1155/1999/54564","mag":"2067969908"},"language":"en","primary_location":{"id":"doi:10.1155/1999/54564","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/54564","pdf_url":"https://downloads.hindawi.com/archive/1999/054564.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1999/054564.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064518354","display_name":"Wen-Jer Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wen-Jer Wu","raw_affiliation_strings":["Department of Computer Science, National Tsing-Hua University, Taiwan 300","Vate Technology Co., Ltd., 9 Li-Hsin Rd. V, Science-Based Industrial Park, Taiwan 300"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing-Hua University, Taiwan 300","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"Vate Technology Co., Ltd., 9 Li-Hsin Rd. V, Science-Based Industrial Park, Taiwan 300","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011281958","display_name":"Chuan Tang","orcid":"https://orcid.org/0000-0001-7230-0625"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chuan Yi Tang","raw_affiliation_strings":["Department of Computer Science, National Tsing-Hua University, Taiwan 300"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing-Hua University, Taiwan 300","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5011281958"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15236641,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":"2","first_page":"143","last_page":"153"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9900000095367432,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9855999946594238,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6491228342056274},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6151199340820312},{"id":"https://openalex.org/keywords/linear-programming","display_name":"Linear programming","score":0.5945852994918823},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.569465696811676},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35577884316444397}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6491228342056274},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6151199340820312},{"id":"https://openalex.org/C41045048","wikidata":"https://www.wikidata.org/wiki/Q202843","display_name":"Linear programming","level":2,"score":0.5945852994918823},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.569465696811676},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35577884316444397},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/1999/54564","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/54564","pdf_url":"https://downloads.hindawi.com/archive/1999/054564.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/1999/54564","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/54564","pdf_url":"https://downloads.hindawi.com/archive/1999/054564.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2067969908.pdf","grobid_xml":"https://content.openalex.org/works/W2067969908.grobid-xml"},"referenced_works_count":8,"referenced_works":["https://openalex.org/W289624287","https://openalex.org/W1554885925","https://openalex.org/W1994887588","https://openalex.org/W2114662019","https://openalex.org/W3021483259","https://openalex.org/W4302458519","https://openalex.org/W6649137549","https://openalex.org/W6677316095"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2116677773","https://openalex.org/W2155261584","https://openalex.org/W2051487156","https://openalex.org/W2073681303","https://openalex.org/W2584231425","https://openalex.org/W2042919702","https://openalex.org/W2390279801","https://openalex.org/W2150611273","https://openalex.org/W4207086172"],"abstract_inverted_index":{"In":[0,70],"this":[1],"paper,":[2],"an":[3,98],"automatic":[4],"technique":[5],"for":[6,97],"test":[7,19,40,68,75],"timing":[8,26,41,64,76],"assignment":[9,42,77],"is":[10,13,79],"proposed":[11,72,108],"which":[12,87],"comprehensive":[14],"enough":[15],"to":[16,103],"take":[17],"the":[18,29,56,71,74,107],"objective":[20],"(e.g.,":[21],"strictness":[22],"of":[23,66,93,106],"selected":[24],"AC":[25],"parameters)":[27],"and":[28,35,58,62],"constraints":[30],"from":[31],"both":[32],"RAM":[33,67],"specification":[34],"tester":[36],"into":[37,81],"consideration.":[38],"Since":[39],"problem":[43,78],"could":[44],"only":[45],"be":[46,89],"solved":[47],"manually":[48],"before,":[49],"therefore,":[50],"our":[51],"work":[52],"can":[53,88],"significantly":[54],"reduce":[55],"efforts":[57],"costs":[59],"on":[60],"developing":[61],"maintaining":[63],"modules":[65],"programs.":[69],"technique,":[73],"transformed":[80],"a":[82],"linear":[83],"programming":[84],"(LP)":[85],"model,":[86],"automatically":[90],"solved.":[91],"Examples":[92],"building":[94],"LP":[95],"models":[96],"asynchronous":[99],"DRAM":[100],"are":[101],"given":[102],"show":[104],"feasibility":[105],"technique.":[109]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}