{"id":"https://openalex.org/W2121154718","doi":"https://doi.org/10.1155/1999/38974","title":"Tuning Strategies for Global Interconnectsin High\u2010Performance Deep\u2010Submicron ICs","display_name":"Tuning Strategies for Global Interconnectsin High\u2010Performance Deep\u2010Submicron ICs","publication_year":1998,"publication_date":"1998-11-20","ids":{"openalex":"https://openalex.org/W2121154718","doi":"https://doi.org/10.1155/1999/38974","mag":"2121154718"},"language":"en","primary_location":{"id":"doi:10.1155/1999/38974","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/38974","pdf_url":"https://downloads.hindawi.com/archive/1999/038974.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1999/038974.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073558386","display_name":"Andrew B. Kahng","orcid":"https://orcid.org/0000-0002-4490-5018"},"institutions":[{"id":"https://openalex.org/I4210156583","display_name":"Laboratoire d'Informatique de Paris-Nord","ror":"https://ror.org/05g1zjw44","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210091279","https://openalex.org/I4210156583","https://openalex.org/I4210159245"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Andrew B. Kahng","raw_affiliation_strings":["UCLA Computer Science Dept., 3713 Boelter Hall"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"UCLA Computer Science Dept., 3713 Boelter Hall","institution_ids":["https://openalex.org/I4210156583"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050535285","display_name":"S. Muddu","orcid":null},"institutions":[{"id":"https://openalex.org/I93085520","display_name":"Silicon Labs (United States)","ror":"https://ror.org/02dyqfb80","country_code":"US","type":"company","lineage":["https://openalex.org/I93085520"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhakar Muddu","raw_affiliation_strings":["Silicon Graphics, lnc., 2011 N. Shoreline Blvd., 40L-175"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Graphics, lnc., 2011 N. Shoreline Blvd., 40L-175","institution_ids":["https://openalex.org/I93085520"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083138709","display_name":"Egino Sarto","orcid":null},"institutions":[{"id":"https://openalex.org/I93085520","display_name":"Silicon Labs (United States)","ror":"https://ror.org/02dyqfb80","country_code":"US","type":"company","lineage":["https://openalex.org/I93085520"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Egino Sarto","raw_affiliation_strings":["Silicon Graphics, lnc., 2011 N. Shoreline Blvd., 40L-175"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Graphics, lnc., 2011 N. Shoreline Blvd., 40L-175","institution_ids":["https://openalex.org/I93085520"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4717,"has_fulltext":true,"cited_by_count":22,"citation_normalized_percentile":{"value":0.82138267,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"10","issue":"1","first_page":"21","last_page":"34"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7622678279876709},{"id":"https://openalex.org/keywords/repeater","display_name":"Repeater (horology)","score":0.7344778776168823},{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.6712496280670166},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.6360760927200317},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5784858465194702},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5725775957107544},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5443432331085205},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.45730477571487427},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4236864447593689},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.41588613390922546},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3938562273979187},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32061123847961426},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16456130146980286}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7622678279876709},{"id":"https://openalex.org/C195545963","wikidata":"https://www.wikidata.org/wiki/Q1469803","display_name":"Repeater (horology)","level":3,"score":0.7344778776168823},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.6712496280670166},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.6360760927200317},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5784858465194702},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5725775957107544},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5443432331085205},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.45730477571487427},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4236864447593689},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.41588613390922546},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3938562273979187},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32061123847961426},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16456130146980286},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/1999/38974","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/38974","pdf_url":"https://downloads.hindawi.com/archive/1999/038974.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.189.4558","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.189.4558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://vlsicad.ucsd.edu/Publications/Journals/j38.pdf","raw_type":"text"}],"best_oa_location":{"id":"doi:10.1155/1999/38974","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1999/38974","pdf_url":"https://downloads.hindawi.com/archive/1999/038974.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869","https://openalex.org/P4310320595"],"host_organization_lineage_names":["Hindawi Publishing Corporation","Wiley"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2121154718.pdf","grobid_xml":"https://content.openalex.org/works/W2121154718.grobid-xml"},"referenced_works_count":19,"referenced_works":["https://openalex.org/W1908785542","https://openalex.org/W1986598762","https://openalex.org/W1988888257","https://openalex.org/W2002159707","https://openalex.org/W2014919362","https://openalex.org/W2036818566","https://openalex.org/W2048312633","https://openalex.org/W2099628065","https://openalex.org/W2099766936","https://openalex.org/W2118891103","https://openalex.org/W2120196821","https://openalex.org/W2162891036","https://openalex.org/W4232340320","https://openalex.org/W4236913175","https://openalex.org/W4252668332","https://openalex.org/W6647585100","https://openalex.org/W6654404474","https://openalex.org/W6659859092","https://openalex.org/W6662583276"],"related_works":["https://openalex.org/W2094969048","https://openalex.org/W994558755","https://openalex.org/W3035935536","https://openalex.org/W2010746423","https://openalex.org/W2372119205","https://openalex.org/W2081032080","https://openalex.org/W2017322750","https://openalex.org/W2134733504","https://openalex.org/W2144460576","https://openalex.org/W1520075683"],"abstract_inverted_index":{"Interconnect":[0],"tuning":[1,75,87,170],"is":[2,49,171],"an":[3],"increasingly":[4],"critical":[5],"degree":[6],"of":[7,13,25,73,97,175,182],"freedom":[8],"in":[9,31,53,63,76,195],"the":[10,23,64,69,77,135,154],"physical":[11],"design":[12,56],"high\u2010performance":[14],"VLSI":[15],"systems.":[16],"By":[17],"interconnect":[18,33,44,74,86,159,164,169],"tuning,":[19],"we":[20],"refer":[21],"to":[22,34,90,118],"selection":[24],"line":[26,124,130],"thicknesses,":[27],"widths":[28],"and":[29,43,46,85,95,103,114],"spacings":[30],"multi\u2010layer":[32],"simultaneously":[35],"optimize":[36],"signal":[37,39,41,101],"distribution,":[38],"performance,":[40],"integrity,":[42],"manufacturability":[45],"reliability.":[47],"This":[48],"a":[50,122,128,179],"key":[51],"activity":[52],"most":[54],"leading\u2010edge":[55],"projects,":[57],"but":[58],"has":[59],"received":[60],"little":[61],"attention":[62],"literature.":[65,78],"Our":[66,173],"work":[67],"provides":[68],"first":[70],"technology\u2010specific":[71],"studies":[72],"We":[79,105],"center":[80],"on":[81],"global":[82,145,163],"wiring":[83],"layers":[84],"issues":[88],"related":[89],"bus":[91],"routing,":[92],"repeater":[93,184],"insertion,":[94],"choice":[96],"shielding/spacing":[98],"rules":[99],"for":[100,121,157],"integrity":[102],"performance.":[104],"address":[106],"four":[107],"basic":[108],"questions.":[109],"(1)":[110],"How":[111],"should":[112],"width":[113],"spacing":[115],"be":[116,142],"allocated":[117],"maximize":[119],"performance":[120],"given":[123,129],"pitch?":[125],"(2)":[126],"For":[127],"pitch,":[131],"what":[132,149,167],"criteria":[133],"affect":[134],"optimal":[136],"interval":[137],"at":[138],"which":[139],"repeaters":[140],"Should":[141],"inserted":[143],"into":[144],"interconnects?":[146],"(3)":[147],"Under":[148],"circumstances":[150],"are":[151],"shield":[152],"wires":[153],"optimum":[155],"technique":[156],"improving":[158],"performance?":[160],"(4)":[161,177],"In":[162],"with":[165],"repeaters,":[166],"other":[168],"possible?":[172],"study":[174],"question":[176],"demonstrates":[178],"new":[180],"approach":[181],"offsetting":[183],"placements":[185],"that":[186],"can":[187],"reduce":[188],"worst\u2010case":[189],"cross\u2010chip":[190],"delays":[191],"by":[192],"over":[193],"30%":[194],"current":[196],"technologies.":[197]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}