{"id":"https://openalex.org/W2025525725","doi":"https://doi.org/10.1155/1998/82084","title":"Topologically Rectangular Grids in the Parallel Simulationof Semiconductor Devices","display_name":"Topologically Rectangular Grids in the Parallel Simulationof Semiconductor Devices","publication_year":1998,"publication_date":"1998-01-01","ids":{"openalex":"https://openalex.org/W2025525725","doi":"https://doi.org/10.1155/1998/82084","mag":"2025525725"},"language":"en","primary_location":{"id":"doi:10.1155/1998/82084","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/82084","pdf_url":"https://downloads.hindawi.com/archive/1998/082084.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1998/082084.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016091223","display_name":"Asen Asenov","orcid":"https://orcid.org/0000-0002-9567-6366"},"institutions":[{"id":"https://openalex.org/I7882870","display_name":"University of Glasgow","ror":"https://ror.org/00vtgdb53","country_code":"GB","type":"education","lineage":["https://openalex.org/I7882870"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"A. Asenov","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow","institution_ids":["https://openalex.org/I7882870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102906680","display_name":"Andrew R. Brown","orcid":"https://orcid.org/0000-0003-4471-7129"},"institutions":[{"id":"https://openalex.org/I7882870","display_name":"University of Glasgow","ror":"https://ror.org/00vtgdb53","country_code":"GB","type":"education","lineage":["https://openalex.org/I7882870"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A. R. Brown","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow","institution_ids":["https://openalex.org/I7882870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070060702","display_name":"S. Roy","orcid":"https://orcid.org/0000-0002-2238-9542"},"institutions":[{"id":"https://openalex.org/I7882870","display_name":"University of Glasgow","ror":"https://ror.org/00vtgdb53","country_code":"GB","type":"education","lineage":["https://openalex.org/I7882870"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"S. Roy","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow","institution_ids":["https://openalex.org/I7882870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005198907","display_name":"John R. Barker","orcid":"https://orcid.org/0000-0001-9248-2470"},"institutions":[{"id":"https://openalex.org/I7882870","display_name":"University of Glasgow","ror":"https://ror.org/00vtgdb53","country_code":"GB","type":"education","lineage":["https://openalex.org/I7882870"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"J. R. Barker","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow","institution_ids":["https://openalex.org/I7882870"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5016091223"],"corresponding_institution_ids":["https://openalex.org/I7882870"],"apc_list":null,"apc_paid":null,"fwci":0.7376,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.73325183,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"1-4","first_page":"91","last_page":"95"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9882000088691711,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9882000088691711,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.984000027179718,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9825999736785889,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mimd","display_name":"MIMD","score":0.8739786148071289},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6654201149940491},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.603144109249115},{"id":"https://openalex.org/keywords/discretization","display_name":"Discretization","score":0.5904589295387268},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.5696015357971191},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5647702217102051},{"id":"https://openalex.org/keywords/mesh-generation","display_name":"Mesh generation","score":0.4335673451423645},{"id":"https://openalex.org/keywords/grid","display_name":"Grid","score":0.4166056513786316},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3219473958015442},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.25715214014053345},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.13335368037223816},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11948487162590027},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11225429177284241},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10431963205337524},{"id":"https://openalex.org/keywords/finite-element-method","display_name":"Finite element method","score":0.07655304670333862}],"concepts":[{"id":"https://openalex.org/C21032095","wikidata":"https://www.wikidata.org/wiki/Q1149237","display_name":"MIMD","level":2,"score":0.8739786148071289},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6654201149940491},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.603144109249115},{"id":"https://openalex.org/C73000952","wikidata":"https://www.wikidata.org/wiki/Q17007827","display_name":"Discretization","level":2,"score":0.5904589295387268},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.5696015357971191},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5647702217102051},{"id":"https://openalex.org/C181145010","wikidata":"https://www.wikidata.org/wiki/Q4418033","display_name":"Mesh generation","level":3,"score":0.4335673451423645},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.4166056513786316},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3219473958015442},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.25715214014053345},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.13335368037223816},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11948487162590027},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11225429177284241},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10431963205337524},{"id":"https://openalex.org/C135628077","wikidata":"https://www.wikidata.org/wiki/Q220184","display_name":"Finite element method","level":2,"score":0.07655304670333862},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/1998/82084","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/82084","pdf_url":"https://downloads.hindawi.com/archive/1998/082084.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/1998/82084","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/82084","pdf_url":"https://downloads.hindawi.com/archive/1998/082084.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2025525725.pdf","grobid_xml":"https://content.openalex.org/works/W2025525725.grobid-xml"},"referenced_works_count":5,"referenced_works":["https://openalex.org/W757979532","https://openalex.org/W2030887004","https://openalex.org/W2056760934","https://openalex.org/W2147632862","https://openalex.org/W4247880210"],"related_works":["https://openalex.org/W3022216878","https://openalex.org/W1533752153","https://openalex.org/W2296577031","https://openalex.org/W2587686085","https://openalex.org/W2355719877","https://openalex.org/W2478182825","https://openalex.org/W1669193437","https://openalex.org/W70893980","https://openalex.org/W2310488688","https://openalex.org/W3129860916"],"abstract_inverted_index":{"Topologically":[0],"rectangular":[1,31,88],"grids":[2,43,64,89],"offer":[3],"simplicity":[4],"and":[5,33,62,79],"efficiency":[6],"in":[7],"the":[8,27,39,58,74,93],"design":[9],"of":[10,29,38,41,60,69,86,95],"parallel":[11,76],"semiconductor":[12],"device":[13,98],"simulators":[14],"tailored":[15],"for":[16],"mesh":[17],"connected":[18],"MIMD":[19],"platforms.":[20],"This":[21],"paper":[22],"presents":[23],"several":[24],"approaches":[25],"to":[26,56,73],"generation":[28,78],"topologically":[30,87],"2D":[32,61],"3D":[34,63],"grids.":[35],"The":[36,84],"effects":[37],"partitioning":[40,59],"such":[42],"on":[44,65],"different":[45],"processor":[46],"configurations":[47],"are":[48,82],"studied.":[49],"A":[50],"simulated":[51],"annealing":[52],"algorithm":[53],"is":[54,90],"used":[55],"optimise":[57],"two":[66],"dimensional":[67],"arrays":[68],"processors.":[70],"Problems":[71],"related":[72],"discretization,":[75],"matrix":[77],"solution":[80],"strategy":[81],"discussed.":[83],"use":[85],"illustrated":[91],"through":[92],"example":[94],"power":[96],"electronic":[97],"simulation.":[99]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
