{"id":"https://openalex.org/W2132214684","doi":"https://doi.org/10.1155/1998/57380","title":"Performance and Wirability Driven Layout for Row\u2010Based FPGAs","display_name":"Performance and Wirability Driven Layout for Row\u2010Based FPGAs","publication_year":1995,"publication_date":"1995-07-10","ids":{"openalex":"https://openalex.org/W2132214684","doi":"https://doi.org/10.1155/1998/57380","mag":"2132214684"},"language":"en","primary_location":{"id":"doi:10.1155/1998/57380","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/57380","pdf_url":"https://downloads.hindawi.com/archive/1998/057380.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1998/057380.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110750075","display_name":"Sudip Nag","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sudip Nag","raw_affiliation_strings":["xilinx Inc., 2100 Logic Drive"],"affiliations":[{"raw_affiliation_string":"xilinx Inc., 2100 Logic Drive","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["Electrical and Computer Engineering, Purdue University"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Purdue University","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5110750075"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20502683,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"4","first_page":"353","last_page":"364"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.672966480255127},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5958628058433533},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47316011786460876},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44551989436149597},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36719515919685364},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.32001206278800964}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.672966480255127},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5958628058433533},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47316011786460876},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44551989436149597},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36719515919685364},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.32001206278800964}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/1998/57380","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/57380","pdf_url":"https://downloads.hindawi.com/archive/1998/057380.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:scholarbank.nus.edu.sg:10635/181142","is_oa":true,"landing_page_url":"https://scholarbank.nus.edu.sg/handle/10635/181142","pdf_url":null,"source":{"id":"https://openalex.org/S7407052290","display_name":"National University of Singapore","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Unpaywall 20201031","raw_type":"Article"}],"best_oa_location":{"id":"doi:10.1155/1998/57380","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/57380","pdf_url":"https://downloads.hindawi.com/archive/1998/057380.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2132214684.pdf","grobid_xml":"https://content.openalex.org/works/W2132214684.grobid-xml"},"referenced_works_count":26,"referenced_works":["https://openalex.org/W1974474301","https://openalex.org/W1984588379","https://openalex.org/W2098851518","https://openalex.org/W2099496765","https://openalex.org/W2102182481","https://openalex.org/W2116059830","https://openalex.org/W2120985183","https://openalex.org/W2128041927","https://openalex.org/W2132275486","https://openalex.org/W2134993085","https://openalex.org/W2139071021","https://openalex.org/W2144514287","https://openalex.org/W2149339848","https://openalex.org/W2156568500","https://openalex.org/W2161455936","https://openalex.org/W2166105055","https://openalex.org/W3217150240","https://openalex.org/W4229698128","https://openalex.org/W4230254537","https://openalex.org/W4242028921","https://openalex.org/W6675768448","https://openalex.org/W6678049473","https://openalex.org/W6680034409","https://openalex.org/W6682377789","https://openalex.org/W6684500659","https://openalex.org/W6804565094"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"In":[0,17,76],"FPGAs":[1],"the":[2,13,19,22,28,43,62,116],"routing":[3],"resources":[4],"are":[5,107],"fixed":[6],"and":[7,45,73,84,99,104,140],"their":[8],"usage":[9],"is":[10,52],"constrained":[11],"by":[12,109],"location":[14],"of":[15,48,137],"antifuses.":[16],"addition,":[18],"antifuses":[20],"affect":[21],"layout":[23,58,63,87],"performance":[24,85],"significantly,":[25],"depending":[26],"on":[27,68],"technology.":[29],"Hence,":[30],"simplistic":[31],"placement":[32,65],"level":[33,66],"assumptions":[34],"turn":[35],"out":[36],"to":[37,113,122,130],"be":[38],"grossly":[39],"inadequate":[40],"in":[41,124],"predicting":[42],"timing":[44,71,97],"wirability":[46,83,100],"behavior":[47],"a":[49,53,57,82,95,135],"layout.":[50],"There":[51],"need,":[54],"therefore,":[55],"for":[56,89,134],"technique":[59],"which":[60],"changes":[61],"at":[64],"based":[67],"accurate":[69],"post\u2010layout":[70,96],"analysis":[72],"net":[74],"wirability.":[75],"this":[77],"paper":[78],"we":[79],"consider":[80],"such":[81],"driven":[86],"flow":[88],"row\u2010based":[90],"FPGAs.":[91],"Timing":[92],"information":[93,101],"from":[94,102],"analyzer":[98],"global":[103],"channel":[105],"routers":[106],"used":[108],"an":[110],"incremental":[111],"placer":[112],"effectively":[114],"perturb":[115],"placement.":[117],"A":[118],"large":[119],"improvement":[120],"(up":[121],"29%)":[123],"timing,":[125],"has":[126],"been":[127],"obtained":[128],"(compared":[129],"non\u2010iterative":[131],"FPGA":[132],"layout)":[133],"set":[136],"industrial":[138],"designs":[139],"benchmark":[141],"examples.":[142]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
