{"id":"https://openalex.org/W1968035060","doi":"https://doi.org/10.1155/1998/49145","title":"Timing\u2010Driven Circuit Implementation","display_name":"Timing\u2010Driven Circuit Implementation","publication_year":1998,"publication_date":"1998-01-01","ids":{"openalex":"https://openalex.org/W1968035060","doi":"https://doi.org/10.1155/1998/49145","mag":"1968035060"},"language":"en","primary_location":{"id":"doi:10.1155/1998/49145","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/49145","pdf_url":null,"source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1155/1998/49145","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043196208","display_name":"Dimitrios Karayiannis","orcid":"https://orcid.org/0000-0003-4142-2392"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Dimitrios Karayiannis","raw_affiliation_strings":["Viewlogic Systems Inc., Fremont, CA 94538-6530, USA"],"affiliations":[{"raw_affiliation_string":"Viewlogic Systems Inc., Fremont, CA 94538-6530, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083284025","display_name":"Spyros Tragoudas","orcid":"https://orcid.org/0009-0006-2575-3588"},"institutions":[{"id":"https://openalex.org/I110378019","display_name":"Southern Illinois University Carbondale","ror":"https://ror.org/049kefs16","country_code":"US","type":"education","lineage":["https://openalex.org/I110378019","https://openalex.org/I2801502357"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Spyros Tragoudas","raw_affiliation_strings":["Computer Science Department, 2130 Faner Hall, Southern Illinois University at Carbondale, Carbondale, IL 62901, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science Department, 2130 Faner Hall, Southern Illinois University at Carbondale, Carbondale, IL 62901, USA","institution_ids":["https://openalex.org/I110378019"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5043196208"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06912359,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"2","first_page":"211","last_page":"224"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5637077689170837},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41992950439453125},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.340248167514801},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18519482016563416}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5637077689170837},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41992950439453125},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.340248167514801},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18519482016563416}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1155/1998/49145","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/49145","pdf_url":null,"source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1155/1998/49145","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1998/49145","pdf_url":null,"source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2291886183","display_name":null,"funder_award_id":"MIP-9409905","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1486898914","https://openalex.org/W1982882434","https://openalex.org/W1987786682","https://openalex.org/W1988118342","https://openalex.org/W2006152335","https://openalex.org/W2087656024","https://openalex.org/W2106950603","https://openalex.org/W2133390788","https://openalex.org/W2150985898","https://openalex.org/W2157661053","https://openalex.org/W2158927558","https://openalex.org/W2164832473","https://openalex.org/W2752885492"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052","https://openalex.org/W2382290278","https://openalex.org/W4395014643"],"abstract_inverted_index":{"We":[0],"consider":[1],"the":[2,6,19,39,43,55,60,79,83,94,110,114,120],"problem":[3,62],"of":[4,9,42,82,113],"selecting":[5],"proper":[7],"implementation":[8],"each":[10],"circuit":[11],"module":[12,46,74],"from":[13,25],"a":[14,87,107],"cell":[15],"library":[16],"to":[17,29,34],"minimize":[18],"propagation":[20],"delay":[21],"along":[22],"every":[23],"path":[24],"any":[26,30],"primary":[27,31],"input":[28],"output":[32],"subject":[33],"an":[35],"upper":[36],"bound":[37,108],"on":[38,54,78,98,109,119],"total":[40,111],"area":[41,81,112],"circuit.":[44,84],"Different":[45],"implementations":[47,72],"may":[48,105],"have":[49],"different":[50],"areas":[51],"and":[52,75],"delays":[53],"paths.":[56],"Wc":[57,85],"show":[58],"that":[59],"latter":[61],"is":[63,117],"NP\u2010hard":[64],"even":[65],"for":[66,92],"directed":[67],"acyclic":[68],"graphs":[69],"with":[70],"two":[71],"per":[73],"no":[76],"restrictions":[77],"overall":[80],"present":[86],"novel":[88],"retiming":[89],"based":[90],"heuristic":[91],"determining":[93],"minimum":[95],"clock":[96],"period":[97],"sequential":[99],"circuits":[100],".":[101],"Although":[102],"our":[103],"heuristics":[104],"handle":[106],"circuit,":[115],"emphasis":[116],"given":[118],"timing":[121],"issue.":[122]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
