{"id":"https://openalex.org/W1998449406","doi":"https://doi.org/10.1155/1996/95942","title":"DP\u2010FPGA: An FPGA Architecture Optimized for Datapaths","display_name":"DP\u2010FPGA: An FPGA Architecture Optimized for Datapaths","publication_year":1996,"publication_date":"1996-01-01","ids":{"openalex":"https://openalex.org/W1998449406","doi":"https://doi.org/10.1155/1996/95942","mag":"1998449406"},"language":"en","primary_location":{"id":"doi:10.1155/1996/95942","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1996/95942","pdf_url":"https://downloads.hindawi.com/archive/1996/095942.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1996/095942.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080389688","display_name":"Don Cherepacha","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Don Cherepacha","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041744404","display_name":"David Lewis","orcid":"https://orcid.org/0000-0003-4151-0499"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"David Lewis","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5080389688"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":2.4876,"has_fulltext":true,"cited_by_count":55,"citation_normalized_percentile":{"value":0.90349724,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"4","issue":"4","first_page":"329","last_page":"343"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.926950216293335},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7706409692764282},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7101460099220276},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.6353598833084106},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5516610145568848},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5021951198577881},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.49835658073425293},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4558713138103485},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4109848141670227},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3534805178642273},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09825864434242249}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.926950216293335},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7706409692764282},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7101460099220276},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.6353598833084106},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5516610145568848},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5021951198577881},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.49835658073425293},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4558713138103485},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4109848141670227},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3534805178642273},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09825864434242249},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1155/1996/95942","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1996/95942","pdf_url":"https://downloads.hindawi.com/archive/1996/095942.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:utoronto.scholaris.ca:1807/82224","is_oa":true,"landing_page_url":"http://hdl.handle.net/1807/82224","pdf_url":"https://utoronto.scholaris.ca/bitstreams/08956e54-a08b-425b-9145-c6579835bd42/download","source":{"id":"https://openalex.org/S7407055458","display_name":"TSpace","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"}],"best_oa_location":{"id":"doi:10.1155/1996/95942","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1996/95942","pdf_url":"https://downloads.hindawi.com/archive/1996/095942.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1998449406.pdf","grobid_xml":"https://content.openalex.org/works/W1998449406.grobid-xml"},"referenced_works_count":7,"referenced_works":["https://openalex.org/W1597088765","https://openalex.org/W1674272258","https://openalex.org/W2102341772","https://openalex.org/W2113764809","https://openalex.org/W2114258728","https://openalex.org/W2120397377","https://openalex.org/W2167328871"],"related_works":["https://openalex.org/W2064528241","https://openalex.org/W3095609119","https://openalex.org/W2107701025","https://openalex.org/W2065192738","https://openalex.org/W2142623358","https://openalex.org/W1998449406","https://openalex.org/W1522277080","https://openalex.org/W2138867958","https://openalex.org/W826229029","https://openalex.org/W1994337165"],"abstract_inverted_index":{"This":[0,26,76],"paper":[1,77],"presents":[2],"a":[3,35,96,108,115,141,148,153,159,182,189,196],"new":[4],"Field\u2010Programmable":[5],"Gate":[6,19],"Array":[7],"(FPGA)":[8],"architecture":[9],"which":[10],"reduces":[11],"the":[12,69,79,130,133,138,179,200],"density":[13],"gap":[14],"between":[15],"FPGAs":[16],"and":[17,53,84,122,164,168],"Mask\u2010Programmed":[18],"Arrays":[20],"(MPGAs)":[21],"for":[22,50],"datapath":[23,184],"oriented":[24],"circuits.":[25],"is":[27],"primarily":[28],"achieved":[29],"by":[30,61,188],"operating":[31],"on":[32],"data":[33,54],"as":[34,105,107],"number":[36,71,97,110],"of":[37,48,72,81,98,102,111,118,174,181,191,202],"identically":[38],"programmed":[39],"four\u2010bit":[40,66,155,160],"slices.":[41],"The":[42],"interconnection":[43],"network":[44],"incorporates":[45],"distinct":[46],"sets":[47],"resources":[49],"routing":[51,85],"control":[52],"signals.":[55],"These":[56],"features":[57],"reduce":[58],"circuit":[59],"area":[60,136,176,180],"sharing":[62],"programming":[63,203],"bits":[64],"among":[65],"slices,":[67],"reducing":[68],"total":[70],"storage":[73],"cells":[74],"required.":[75],"discusses":[78],"requirements":[80],"logic":[82,119],"blocks":[83],"structures":[86],"that":[87,129,178],"can":[88,185],"be":[89,186],"used":[90],"to":[91,195],"implement":[92],"typical":[93],"circuits":[94],"containing":[95],"regularly":[99],"structured":[100],"datapaths":[101],"various":[103],"sizes,":[104],"well":[106],"small":[109],"irregularities.":[112],"It":[113],"proposes":[114],"specific":[116],"set":[117],"block":[120,131],"architectures":[121],"analyzes":[123],"it":[124],"empirically.":[125],"Experimental":[126],"results":[127],"show":[128],"with":[132,144,162],"smallest":[134],"estimated":[135],"contains":[137],"following":[139],"features:":[140],"lookup":[142],"table":[143],"four":[145,169],"read":[146],"ports,":[147],"dedicated":[149],"carry":[150,156],"chain":[151],"using":[152],"bidirectional":[154],"skip":[157],"circuit,":[158],"register":[161],"enable":[163],"direct":[165],"input":[166],"capabilities,":[167],"three\u2010state":[170],"buffers.":[171],"Further":[172],"estimates":[173],"implementation":[175],"predict":[177],"design\u2032s":[183],"reduced":[187],"factor":[190],"approximately":[192],"two":[193],"compared":[194],"conventional":[197],"FPGA":[198],"through":[199],"use":[201],"bit":[204],"sharing.":[205]},"counts_by_year":[{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-08T08:50:53.379069","created_date":"2025-10-10T00:00:00"}
