{"id":"https://openalex.org/W2121092778","doi":"https://doi.org/10.1155/1995/76861","title":"Stepwise Transformation of Algorithmsinto Array Processor Architecturesby the DECOMP","display_name":"Stepwise Transformation of Algorithmsinto Array Processor Architecturesby the DECOMP","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W2121092778","doi":"https://doi.org/10.1155/1995/76861","mag":"2121092778"},"language":"en","primary_location":{"id":"doi:10.1155/1995/76861","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/76861","pdf_url":"https://downloads.hindawi.com/archive/1995/076861.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/1995/076861.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051885742","display_name":"Uwe Vehlies","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Uwe Vehlies","raw_affiliation_strings":["Laboratorium f\u00fcr Informationstechnologie, University of Hannover Schneiderberg 32"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratorium f\u00fcr Informationstechnologie, University of Hannover Schneiderberg 32","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5051885742"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3834,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.67956533,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":"1","first_page":"67","last_page":"80"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7930819988250732},{"id":"https://openalex.org/keywords/transformation","display_name":"Transformation (genetics)","score":0.6315881013870239},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5863766670227051},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5046850442886353},{"id":"https://openalex.org/keywords/processor-array","display_name":"Processor array","score":0.4636337459087372},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.4392378032207489},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4326990842819214},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.4128410518169403},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.41035449504852295},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32585209608078003}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7930819988250732},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.6315881013870239},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5863766670227051},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5046850442886353},{"id":"https://openalex.org/C2776189500","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Processor array","level":2,"score":0.4636337459087372},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.4392378032207489},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4326990842819214},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.4128410518169403},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.41035449504852295},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32585209608078003},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1155/1995/76861","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/76861","pdf_url":"https://downloads.hindawi.com/archive/1995/076861.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:www.repo.uni-hannover.de:123456789/2045","is_oa":true,"landing_page_url":"http://www.repo.uni-hannover.de/handle/123456789/2045","pdf_url":null,"source":{"id":"https://openalex.org/S4306401575","display_name":"Institutional Repository of Leibniz Universit\u00e4t Hannover (Leibniz Universit\u00e4t Hannover)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I114112103","host_organization_name":"Leibniz University Hannover","host_organization_lineage":["https://openalex.org/I114112103"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Vlsi Design 3 (1995), Nr. 1","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"doi:10.15488/2020","is_oa":true,"landing_page_url":"https://doi.org/10.15488/2020","pdf_url":null,"source":{"id":"https://openalex.org/S7407052956","display_name":"Leibniz Universit\u00e4t Hannover","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article-journal"}],"best_oa_location":{"id":"doi:10.1155/1995/76861","is_oa":true,"landing_page_url":"https://doi.org/10.1155/1995/76861","pdf_url":"https://downloads.hindawi.com/archive/1995/076861.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2121092778.pdf","grobid_xml":"https://content.openalex.org/works/W2121092778.grobid-xml"},"referenced_works_count":27,"referenced_works":["https://openalex.org/W29642719","https://openalex.org/W90180915","https://openalex.org/W1483931739","https://openalex.org/W1491178396","https://openalex.org/W1617489376","https://openalex.org/W1618677125","https://openalex.org/W1820065643","https://openalex.org/W1964556228","https://openalex.org/W1987632834","https://openalex.org/W2064130185","https://openalex.org/W2079092669","https://openalex.org/W2082333700","https://openalex.org/W2099216186","https://openalex.org/W2099876805","https://openalex.org/W2118435272","https://openalex.org/W2127784257","https://openalex.org/W2139378242","https://openalex.org/W2168986561","https://openalex.org/W2422041157","https://openalex.org/W2743895980","https://openalex.org/W4232179104","https://openalex.org/W4234407207","https://openalex.org/W4236506211","https://openalex.org/W4285719527","https://openalex.org/W6666425473","https://openalex.org/W6675053784","https://openalex.org/W6675118222"],"related_works":["https://openalex.org/W1970433854","https://openalex.org/W2023867642","https://openalex.org/W1905852083","https://openalex.org/W575709247","https://openalex.org/W113996306","https://openalex.org/W81589881","https://openalex.org/W2760697131","https://openalex.org/W2418275724","https://openalex.org/W1564191620","https://openalex.org/W1993084860"],"abstract_inverted_index":{"A":[0],"formal":[1,108],"approach":[2,71,109],"for":[3,89,120],"the":[4,22,54,59,69,107,111],"transformation":[5,43],"of":[6,61,106],"computation":[7],"intensive":[8],"digital":[9],"signal":[10],"processing":[11],"algorithms":[12,74],"into":[13,47],"suitable":[14],"array":[15,79,90],"processor":[16,80,91],"architectures":[17,63],"is":[18,45,93,113],"presented.":[19],"It":[20],"covers":[21],"complete":[23],"design":[24,49,92,118],"flow":[25],"from":[26],"algorithmic":[27],"specifications":[28],"in":[29,37,53,64,110],"a":[30,38,65,85],"high\u2010level":[31],"programming":[32],"language":[33],"to":[34,95],"architecture":[35],"descriptions":[36],"hardware":[39],"description":[40],"language.":[41],"The":[42,104],"itself":[44],"divided":[46],"manageable":[48],"steps":[50],"and":[51],"implemented":[52],"CAD\u2010tool":[55],"DECOMP":[56,112],"which":[57],"allows":[58],"exploration":[60],"different":[62],"short":[66],"time.":[67],"With":[68],"presented":[70],"data":[72,102],"independent":[73],"can":[75],"be":[76],"mapped":[77],"onto":[78],"architectures.":[81],"To":[82],"allow":[83],"this,":[84],"known":[86],"mapping":[87],"methodology":[88],"extended":[94],"handle":[96],"inhomogeneous":[97],"dependence":[98],"graphs":[99],"with":[100],"nonregular":[101],"dependences.":[103],"implementation":[105],"an":[114],"important":[115],"step":[116],"towards":[117],"automation":[119],"massively":[121],"parallel":[122],"systems.":[123]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2016-06-24T00:00:00"}